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1. 发明申请

US20080020546A1 PROCESS FOR INTERFACIAL ADHESION IN LAMINATE STRUCTURES THROUGH PATTERNED ROUGHING OF A SURFACE 有权
标题翻译：通过表面粗糙化的层压结构中的界面粘合方法
公开(公告)号：US20080020546A1
公开(公告)日：2008-01-24
申请号：US11862706
申请日：2007-09-27
申请人： Edward COONEY , Vincent McGahay , Thomas Shaw , Anthony Stamper , Matthew Colburn
发明人： Edward COONEY , Vincent McGahay , Thomas Shaw , Anthony Stamper , Matthew Colburn
IPC分类号： H01L21/475 , H01L21/302 , H01L21/32 , H01L21/467
CPC分类号： H01L21/76829 , H01L21/31144 , H01L21/76828 , H01L21/78
摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.
摘要翻译：本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

2. 发明申请

US20050277266A1 PROCESS FOR INTERFACIAL ADHESION IN LAMINATE STRUCTURES THROUGH PATTERNED ROUGHING OF A SURFACE 失效
标题翻译：通过表面粗糙化的层压结构中的界面粘合方法
公开(公告)号：US20050277266A1
公开(公告)日：2005-12-15
申请号：US10710034
申请日：2004-06-14
申请人： Edward Cooney , Vincent McGahay , Thomas Shaw , Anthony Stamper , Matthew Colburn
发明人： Edward Cooney , Vincent McGahay , Thomas Shaw , Anthony Stamper , Matthew Colburn
IPC分类号： C23C14/00 , C23C14/32 , H01L21/30 , H01L21/302 , H01L21/311 , H01L21/46 , H01L21/461 , H01L21/768 , H01L21/78
CPC分类号： H01L21/76829 , H01L21/31144 , H01L21/76828 , H01L21/78
摘要： The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.
摘要翻译：本发明涉及使用图案化粗糙化改善电介质的界面粘附的方法。可以通过增加材料之间的界面的粗糙度来实现层和基底之间的改善的粘附强度。粗糙度可能包括任何干扰通常平滑的表面，如凹槽，凹痕，孔，沟槽等。可以通过在衬底的表面上沉积材料作为掩模，然后使用蚀刻工艺来引起粗糙度来实现界面上的粗加工。用作掩模的材料允许蚀刻在以常规光掩模和光刻实现的规模以下的精细或次微小尺度上发生，以实现所需的图案粗糙化。然后将另一种材料沉积在基底的粗糙表面上，填充粗加工并粘附到基底上。

3. 发明申请

US20050167838A1 DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于减少半导体器件中有效介电常数的器件和方法
公开(公告)号：US20050167838A1
公开(公告)日：2005-08-04
申请号：US10707996
申请日：2004-01-30
申请人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
发明人： Daniel Edelstein , Matthew Colburn , Edward Cooney , Timothy Dalton , John Fitzsimmons , Jeffrey Gambino , Elbert Huang , Michael Lane , Vincent McGahay , Lee Nicholson , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas Shaw , Andrew Simon , Anthony Stamper
IPC分类号： H01L21/033 , H01L21/302 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lanes and vias
摘要翻译：一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。还可以使用超光刻阻挡掩模。另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。可能禁止在划线车道和通道上或附近形成间隙

4. 发明申请

US20060258159A1 Process for preparing electronics structures using a sacrificial multilayer hardmask scheme 有权
标题翻译：使用牺牲多层硬掩模方案制备电子结构的方法
公开(公告)号：US20060258159A1
公开(公告)日：2006-11-16
申请号：US11130078
申请日：2005-05-16
申请人： Matthew Colburn , Ricardo Donaton , Conal Murray , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Theodorus Eduardus Fransiscus Standaert , Xiao Liu
发明人： Matthew Colburn , Ricardo Donaton , Conal Murray , Satyanarayana Nitta , Sampath Purushothaman , Sujatha Sankaran , Theodorus Eduardus Fransiscus Standaert , Xiao Liu
IPC分类号： H01B13/00 , H01L21/302 , B44C1/22
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/31144 , H01L21/7682
摘要： A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.
摘要翻译：用于制备电子结构的方法包括用牺牲多层硬掩模堆叠涂覆衬底叠层，在涂覆在多层硬掩模堆叠的最上层上的抗蚀剂层中形成图案，将图案转移到硬掩模堆叠中，阻挡部分图案，然后将图案的未封闭部分转印到基底叠层中。使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。要强调的是，该摘要被提供以符合要求抽象的规则，这将允许搜索者或其他读者快速地确定技术公开的主题。提交它的理解是，它不会用于解释或限制所附权利要求的范围或含义。

5. 发明申请

US20060244146A1 Method for improved process latitude by elongated via integration 失效
标题翻译：通过扩展通过集成改进工艺纬度的方法
公开(公告)号：US20060244146A1
公开(公告)日：2006-11-02
申请号：US11474420
申请日：2006-06-26
申请人： Matthew Colburn
发明人： Matthew Colburn
IPC分类号： H01L23/52
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/7681 , H01L21/76829
摘要： Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.
摘要翻译：互连双镶嵌结构通过沉积在至少一个介电层的层上制造，掩模形成层用于提供双镶嵌结构的通孔级掩模层; 在通孔级掩模层中形成细长的通孔图案; 沉积一层线路电介质并通过线路级电介质层产生线路图案，并且通过细长通孔电平图案和线路电平图案的投影交点传送线路图案，从而产生对准的双大马士革结构。导电衬里层沉积在双镶嵌结构中，然后用导电填充金属填充双镶嵌结构以形成一组金属线。金属和衬里层被平坦化。

6. 发明申请

US20060228653A1 DEVELOPMENT OR REMOVAL OF BLOCK COPOLYMER OR PMMA-b-S-BASED RESIST USING POLAR SUPERCRITICAL SOLVENT 有权
标题翻译：使用极性超临界溶剂开发或去除嵌段共聚物或PMMA-b-S基电阻
公开(公告)号：US20060228653A1
公开(公告)日：2006-10-12
申请号：US10907688
申请日：2005-04-12
申请人： Matthew Colburn , Dmitriy Shneyder , Shahab Siddiqui
发明人： Matthew Colburn , Dmitriy Shneyder , Shahab Siddiqui
IPC分类号： G03C5/00
CPC分类号： G03F7/168 , G03F7/325 , Y10S438/922 , Y10S977/733 , Y10S977/734
摘要： Methods of developing or removing a select region of block copolymer films using a polar supercritical solvent to dissolve a select portion are disclosed. In one embodiment, the polar supercritical solvent includes chlorodifluoromethane, which may be exposed to the block copolymer film using supercritical carbon dioxide (CO2) as a carrier or chlorodiflouromethane itself in supercritical form. The invention also includes a method of forming a nano-structure including exposing a polymeric film to a polar supercritical solvent to develop at least a portion of the polymeric film. The invention also includes a method of removing a poly(methyl methacrylate-b-styrene) (PMMA-b-S) based resist using a polar supercritical solvent.
摘要翻译：公开了使用极性超临界溶剂显影或除去嵌段共聚物膜的选择区域以溶解选择部分的方法。在一个实施方案中，极性超临界溶剂包括氯二氟甲烷，其可以使用超临界二氧化碳（CO 2 CO 2）作为载体或氯二氟乙烷本身以超临界形式暴露于嵌段共聚物膜。本发明还包括形成纳米结构的方法，包括将聚合物膜暴露于极性超临界溶剂以形成至少一部分聚合物膜。本发明还包括使用极性超临界溶剂除去聚（甲基丙烯酸甲酯-b-苯乙烯）（PMMA-b-S）基抗蚀剂的方法。

7. 发明申请

US20060157898A1 Imprint reference template for multilayer or multipattern registration and method therefor 审中-公开
标题翻译：用于多层或多模式注册的印刷参考模板及其方法
公开(公告)号：US20060157898A1
公开(公告)日：2006-07-20
申请号：US11037890
申请日：2005-01-18
申请人： Matthew Colburn , Yves Martin , Charles Rettner , Theodore van Kessel , Hematha Wickramasinghe
发明人： Matthew Colburn , Yves Martin , Charles Rettner , Theodore van Kessel , Hematha Wickramasinghe
IPC分类号： B29C35/08
CPC分类号： G03F7/0002 , B01D2239/045 , B82Y10/00 , B82Y40/00 , G03F9/7011 , G03F9/7019
摘要： A method (and resultant structure) of forming a plurality of masks, includes creating a reference template, using imprint lithography to print at least one reference template alignment mark on all of a plurality of mask blanks for a given chip set, and printing sub-patterns on each of the plurality of mask blanks, and aligning the sub-patterns to the at least one reference template alignment mark.
摘要翻译：一种形成多个掩模的方法（和结果）包括使用压印光刻法创建参考模板以在给定芯片组的所有多个掩模坯料上打印至少一个参考模板对准标记，所述多个掩模坯料中的每一个上的图案，以及将所述子图案对准所述至少一个参考模板对准标记。

8. 发明申请

US20060110890A1 Cut-and-paste imprint lithographic mold and method therefor 有权
标题翻译：切割和糊化印刷光刻模具及其方法
公开(公告)号：US20060110890A1
公开(公告)日：2006-05-25
申请号：US10992072
申请日：2004-11-19
申请人： Matthew Colburn , Yves Martin , Theodore van Kessel , Hematha K. Wickramasinghe
发明人： Matthew Colburn , Yves Martin , Theodore van Kessel , Hematha K. Wickramasinghe
IPC分类号： H01L21/76
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure.
摘要翻译：在结构上复制图案的方法（和装置）包括使用压印光刻将形成在第一结构上的图案复制到第二结构的一部分上。

9. 发明申请

US20050233597A1 Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same 审中-公开
标题翻译：用于制备自对准掩模的非光刻方法，由相同制备的制品和用于其的组合物
公开(公告)号：US20050233597A1
公开(公告)日：2005-10-20
申请号：US11143793
申请日：2005-06-02
申请人： Matthew Colburn , Stephen Gates , Jeffrey Hedrick , Elbert Huang , Satyanarayana Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
发明人： Matthew Colburn , Stephen Gates , Jeffrey Hedrick , Elbert Huang , Satyanarayana Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
IPC分类号： H01L21/027 , B32B3/00 , G03F7/00 , G03F7/16 , G03F7/26 , H01L21/31 , H01L21/3105 , H01L21/469
CPC分类号： H05K3/0079 , H01L21/0331 , H01L21/76849 , H05K3/282 , H05K2203/1173 , Y10T428/24802
摘要： A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.
摘要翻译：一种用于在衬底上的现有图案上形成自对准图案的方法，包括在载体中涂覆含有掩蔽材料的溶液的涂层，所述掩模材料对现有图案的部分具有亲和力; 并且允许掩模材料的至少一部分优先组装到现有图案的部分。该图案可以由具有第一原子组成的衬底的第一组区域和第二组衬底的区域组成，其具有不同于第一组成的第二原子组成。第一组区域可以包括一个或多个金属元件，并且第二组区域可以包括电介质。可以将第一和第二区域处理成具有不同的表面性质。按照该方法制造的结构。用于练习该方法的组合物。

10. 发明授权

US06842229B2 Imprint lithography template comprising alignment marks 有权
标题翻译：压印光刻模板，包括对准标记
公开(公告)号：US06842229B2
公开(公告)日：2005-01-11
申请号：US10747795
申请日：2003-12-29
申请人： Sidlgata V. Sreenivasan , Byung J. Choi , Matthew Colburn , Todd Bailey
发明人： Sidlgata V. Sreenivasan , Byung J. Choi , Matthew Colburn , Todd Bailey
IPC分类号： G02B5/18 , B29C35/08 , B29C37/00 , G03F7/00 , G03F7/20 , H01L21/027 , G03B27/62 , G03B27/58
CPC分类号： B29C35/0888 , B29C37/0053 , B29C43/003 , B29C43/021 , B29C2035/0827 , B29C2043/025 , B82Y10/00 , B82Y40/00 , G03F7/0002 , G03F9/00 , Y10S101/36 , Y10T428/24802
摘要： A system of determining and correcting alignment during imprint lithography process is described. During an imprint lithographic process the template may be aligned with the substrate by the use of alignment marks disposed on both the template and substrate. The alignment may be determined and corrected for before the layer is processed.
摘要翻译：描述了在压印光刻工艺期间确定和校正对准的系统。在压印光刻工艺期间，模板可以通过使用设置在模板和衬底上的对准标记与衬底对准。可以在层被处理之前确定和校正对准。

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