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    • 1. 发明授权
    • Clock distribution apparatus and processes particularly useful in
multiprocessor systems
    • 时钟分配装置和处理在多处理器系统中特别有用
    • US5293626A
    • 1994-03-08
    • US536270
    • 1990-06-08
    • Edward C. PriestSteven C. BarberKen ShintakuDavid A. HansonDan L. Massopust
    • Edward C. PriestSteven C. BarberKen ShintakuDavid A. HansonDan L. Massopust
    • G06F1/10H04J3/06G06F13/00
    • G06F1/10G06F1/105H04J3/0626
    • Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations. One arrangement for controlling optical skew includes an arrangement of optical elements physically displaceable in a coaxial direction relative to one another. Skew adjustment networks employ a unique composition of coarse and fine selectable delay arrays implemented either by electrical components, optical components, or a combination thereof.
    • 来自主振荡器的时钟脉冲被分布在多处理器计算机系统中,使得它们在彼此极其紧密的时间容限内到达位于模块的操作簇中的大量利用点。 通过直接测量或通过使用已知的标准特性来确定与每个组件,电气或光学连接,电缆等相关联的延迟。 对从主时钟源到最终芯片传送点的初始发散点的每个完整时钟脉冲路径的延时预算进行记录和求和。 能够引入预定量的时间延迟的组件被并入一些或所有时钟脉冲路径中。 调整这些组件以平衡从时钟路径预算确定的差异。 时钟路径单独地或与光学组件组合地实现在电气部件中,或者在基本上所有的光学配置中实现。 用于控制光学偏斜的一种布置包括可以相对于彼此在同轴方向物理上移位的光学元件的布置。 倾斜调整网络采用由电气部件,光学部件或其组合实现的粗略和精细可选延迟阵列的独特组合。
    • 7. 发明授权
    • Single layer poly fabrication method and device with shallow
emitter/base junctions and optimized channel stopper
    • 单层多晶制造方法和具有浅发射极/基极结和优化的通道阻塞的装置
    • US4721685A
    • 1988-01-26
    • US853792
    • 1986-04-18
    • Timothy M. LindenfelserDavid A. Hanson
    • Timothy M. LindenfelserDavid A. Hanson
    • H01L21/033H01L21/316H01L21/762H01L21/265H01L21/20H01L21/425
    • H01L21/31654H01L21/033H01L21/76216
    • A method for fabricating high performance bipolar transistors using a single polycrystalline silicon layer whereby horizontally and vertically scaled base/emitter junctions are achieved. In an extrinsic base transistor, a composite sandwich of overlying layers of poly silicon, oxide and nitride are deposited over a substrate containing field oxide isolated monocrystalline transistor sites having buried subcollectors and sinker regions. The composite sandwich is thereafter selectively oxidized to define base, emitter and collector regions with the relative thickness of the composite sandwich and the grown oxide being controlled to assure proper horizontal extrinsic base to emitter spacings and shallow vertical intrinsic base to emitter junctions, upon completing subsequent implant and annealing steps. Each active transistor site is also surrounded by a ring-like, channel stopper which is physically isolated from the channel stopper of each other device.
    • 一种用于制造使用单个多晶硅层的高性能双极晶体管的方法,从而实现水平和垂直缩放的基极/发射极结。 在外部基极晶体管中,在包含具有掩埋子集电极和沉降区的场氧化物隔离的单晶晶体管位置的衬底上沉积多晶硅,氧化物和氮化物的覆盖层的复合夹层。 然后,复合夹心物被选择性地氧化以限定具有复合夹心物的相对厚度的基底,发射极和集电极区域,并且生长的氧化物被控制以确保随后完成的适当的水平外在基极与发射极间隔和浅垂直本征基极到发射极结 植入和退火步骤。 每个有源晶体管的位置也被一个环形的通道阻挡器所围绕,该阻挡器与每个其它装置的通道阻塞物理隔离。