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1. 发明申请

WO0119091A3 CIRCUIT AND METHOD FOR MODIFYING A REGION OF AN ENCODED IMAGE 审中-公开
标题翻译：用于修改编码图像区域的电路和方法
公开(公告)号：WO0119091A3
公开(公告)日：2001-05-10
申请号：PCT/US0024334
申请日：2000-08-31
申请人： EQUATOR TECHNOLOGIES INC , EASWAR VENKAT V , DONNELL JOHN S O , NATARAJAN RAMACHANDRAN , GOVE ROBERT J
发明人： EASWAR VENKAT V , O'DONNELL JOHN S , NATARAJAN RAMACHANDRAN , GOVE ROBERT J
IPC分类号： H04N5/262 , H04N5/445 , H04N7/025 , H04N7/03 , H04N7/035 , H04N7/26
CPC分类号： H04N19/90 , H04N19/27 , H04N19/40 , H04N19/48
摘要： A video processing circuit includes a processor that receives an encoded image having first and second regions, decodes the first region of the image, modifies the decoded first region, and re-encodes the modified first region. Such a circuit allows one to modify a region of an image by decoding and re-encoding only that region instead of the entire image. For example, if one wishes to overlay an EPG on a bottom portion of a video frame, then the circuit can decode only the EPG and the bottom portion of the frame, overlay the decoded EPG on the bottom frame portion, and re-encode the overlaid bottom frame portion. Therefore, this technique often reduces the processing time, and thus the cost and complexity of the processing circuit, as compared to a circuit that decodes and re-encodes the entire frame during an image overlay process.
摘要翻译：视频处理电路包括处理器，该处理器接收具有第一和第二区域的编码图像，解码图像的第一区域，修改解码的第一区域，并且重新编码修改后的第一区域。这样的电路允许通过仅对该区域进行解码和重新编码而不是整个图像来修改图像的区域。例如，如果希望将EPG覆盖在视频帧的底部，则电路可以仅解码EPG和帧的底部，将解码的EPG覆盖在底部帧部分上，并且重新编码覆盖底部框架部分。因此，与在图像重叠处理期间对整个帧进行解码和重新编码的电路相比，该技术通常减少处理时间，并因此减少处理电路的成本和复杂性。

2. 发明专利

CA2134813C FILM-TO-VIDEO FORMAT DETECTION FOR DIGITAL TELEVISION 未知
公开(公告)号：CA2134813C
公开(公告)日：2004-05-25
申请号：CA2134813
申请日：1994-11-01
申请人： GOVE ROBERT J , MEYER RICHARD C , MARSHALL STEPHEN W
发明人： GOVE ROBERT J , MEYER RICHARD C , MARSHALL STEPHEN W
IPC分类号： H04N7/32 , H04N5/44 , H04N7/01 , H04N5/46
摘要： A film-to-video format detector (24) for a digital television receiver (10). The detector (24) receives pixel data from a current field and a second preceding field. It determines a set of pixel difference values, sums them to obtain a field difference value, and compares the field difference value to a threshold. These steps are repeated to obtain a series of field difference indicators. This series is analyzed to determine whether it has a pattern corresponding to a film-to-video format.

3. 发明专利

CA2184129A1 BIT-SPLITTING FOR PULSE WIDTH MODULATED SPATIAL LIGHT MODULATOR 未知
公开(公告)号：CA2184129A1
公开(公告)日：1997-03-01
申请号：CA2184129
申请日：1996-08-26
申请人： DOHERTY DONALD B , DAVIS CARL W , EGAN JOSEPH G , GOVE ROBERT J
发明人： DOHERTY DONALD B , DAVIS CARL W , EGAN JOSEPH G , GOVE ROBERT J
IPC分类号： G02B26/08 , G09G3/20 , G09G3/34 , H04N5/74
摘要： A method of implementing pulse-width modulation in a display system (10, 20) that uses a spatial light modulator (SLM) (15). Each frame of data is divided into bit-planes, each bit-plane having one bit of data for each pixel of the SLM and representing a bit weight of the intensity value to be displayed by the pixels. Each bit-plane has a display time corresponding to a portion of the frame period, with bit-planes of more significant bits having longer portions. Then, the display times for one or more of the more significant bits are segmented so that the data for those bits can be displayed in segments rather than for a continuous time. (FIGURE 3A). The segments are distributed throughout the frame period to reduce visual artifacts. (FIGURE 3B).

4. 发明专利

CA2136478A1 DIGITAL MEMORY FOR DISPLAY SYSTEM USING SPATIAL LIGHT MODULATOR 未知
公开(公告)号：CA2136478A1
公开(公告)日：1995-05-31
申请号：CA2136478
申请日：1994-11-23
申请人： GOVE ROBERT J , URBANUS PAUL M , SAMPSELL JEFFREY B , DOHERTY DONALD B , HASHIMOTO MASASHI
发明人： GOVE ROBERT J , URBANUS PAUL M , SAMPSELL JEFFREY B , DOHERTY DONALD B , HASHIMOTO MASASHI
IPC分类号： G02B26/08 , G06T1/60 , G09G3/20 , G09G3/34 , G09G5/39 , H04N5/66 , H04N5/74 , G09G5/00
摘要： A memory (15) for a digital display system (10) having a spatial light modulator (SLM) (16) that displays data in bit-plane format. The memory (15) has control means (25) for row random access. It also has a set of input registers (31) and two sets of output registers (32), (33). The input registers (31) receive pixel data before it has been processed. The memory (15) delivers this data back to a processor (14) for processing via a first set of output registers (32). After processing, the input registers (31) receive pixel data that has been fully processed and is ready for display. The second set of output registers (33), controlled at their input or output by a bit selector (37), delivers bit-planes of data to the SLM (16).

5. 发明专利

CA2134371C SYSTEM AND METHOD FOR PACKING DATA INTO VIDEO PROCESSOR 未知
公开(公告)号：CA2134371C
公开(公告)日：2004-06-15
申请号：CA2134371
申请日：1994-10-26
申请人： GOVE ROBERT J , DOHERTY DONALD B , MARSHALL STEPHEN W , DAVIS CARL W , EGAN JOSEPH G , MEYER RICHARD C , SAMPSELL JEFFREY B , HEIMBUCH SCOTT D
发明人： GOVE ROBERT J , DOHERTY DONALD B , MARSHALL STEPHEN W , DAVIS CARL W , EGAN JOSEPH G , MEYER RICHARD C , SAMPSELL JEFFREY B , HEIMBUCH SCOTT D
IPC分类号： H04N5/922 , H04N5/14 , H04N5/44 , H04N5/74 , H04N5/937 , H04N7/26 , H04N7/30 , H04N7/50 , H04N11/04 , H04N7/12
摘要： A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexes (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stared in first first in-first out buffer memories (34) and (36), respectively. Multiplexes (38) combines one line from first first in- first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.

6. 发明专利

CA2146884A1 MOTION ADAPTIVE SCAN-RATE CONVERSION USING DIRECTIONAL EDGE INTERPOLATION 未知
公开(公告)号：CA2146884A1
公开(公告)日：1995-10-15
申请号：CA2146884
申请日：1995-04-12
申请人： CLATANOFF TODD , MARKANDEY VISHAL , GOVE ROBERT J , OHARA KAZUHIRO
发明人： CLATANOFF TODD , MARKANDEY VISHAL , GOVE ROBERT J , OHARA KAZUHIRO
IPC分类号： H04N7/01 , G06T7/20 , H04N5/44 , H04N7/64 , H04N7/015
摘要： A method for processing video data to produce a progressively scanned signal from an input of conventional interlaced video. The data is received at a processor (1), used to determine a motion signal (26) over time between field of the data. The motion signal is filtered to reduce errors caused by noise-corrupted video sources and then further filtered to spread out the determined motion signal. Edge information (30) is located and combined with the motion signal to produce an integrated progressive-scan signal (36) for display on a video display device, producing images with sharper edges and motion signals which have a lower susceptibility to noise.

7. 发明专利

CA2134813A1 FILM-TO-VIDEO FORMAT DETECTION FOR DIGITAL TELEVISION 未知
公开(公告)号：CA2134813A1
公开(公告)日：1995-05-03
申请号：CA2134813
申请日：1994-11-01
申请人： GOVE ROBERT J , MEYER RICHARD C , MARSHALL STEPHEN W
发明人： GOVE ROBERT J , MEYER RICHARD C , MARSHALL STEPHEN W
IPC分类号： H04N7/32 , H04N5/44 , H04N7/01 , H04N5/46
摘要： 19 FILM-TO-VIDEO FORMAT DETECTION FOR DIGITAL TELEVISION A film-to-video format detector (24) for a digital television receiver (10). The detector (24) receives pixel data from a current field and a second preceding field. It determines a set of pixel difference values, sums them to obtain a field difference value, and compares the field difference value to a threshold. These steps are repeated to obtain a series of field difference indicators. This series is analyzed to determine whether it has a pattern corresponding to a film-to-video format.

8. 发明专利

CA2138834C VIDEO DISPLAY SYSTEM WITH DIGITAL DE-INTERLACING 未知
公开(公告)号：CA2138834C
公开(公告)日：2004-10-19
申请号：CA2138834
申请日：1994-12-22
申请人： GOVE ROBERT J
发明人： GOVE ROBERT J
IPC分类号： H04N7/01 , H04N5/14 , H04N5/44 , H04N5/74 , G09G5/00
摘要： A line generator (31) for receiving fields of pixel data sampled from a video input signal and for generating additional lines of pixel data so that the display frames will have more lines than the fields. The line generator (31) has a motion detector (31a) that determines, on a pixel by pixel basis, whether some part of the current field is in motion. A motion signal from the motion detector (31a) is used to select between outputs of two or more pixel generators (31b, 31c). One of the pixel generators (31b) provides pixel values that are better suited for display when the image is not in motion. The other pixel generator (31c) provides pixel values that are better suited for display when the image is in motion.

9. 发明专利

CA2139794A1 FRAME PIXEL DATA GENERATION 未知
公开(公告)号：CA2139794A1
公开(公告)日：1995-07-19
申请号：CA2139794
申请日：1995-01-09
申请人： GOVE ROBERT J
发明人： GOVE ROBERT J
IPC分类号： H04N5/74 , H04N5/14 , H04N5/44 , H04N7/01
摘要： A pixel generator and method of generating pixel data for creating frames of video pixel data from fields of input video pixel data. The pixel processor 16 includes a field buffer circuit 36 that stores a plurality of fields of input video pixel data. Coupled to the field buffer are a feature detector 38 and a pixel generator 40. The feature detector 38 generates one or more feature magnitude signals based upon one or more of the fields of input video pixel data. The pixel generator 40 has at least two logic circuits for generating at least two different intermediate pixel data values based on the input pixel data. Coupled to feature detector 38 is feature analyzer 42 that selects a feature weight corresponding to each intermediate pixel data value, the weight being based upon the value of the feature magnitude signals. Coupled to feature analyzer 42 and pixel generator 40, is a pixel averager 44 that generates output pixel data based upon a weighted average of the intermediate pixel data values.

10. 发明专利

CA2134812A1 GRAPHICS SUB-DISPLAYS FOR DIGITAL TELEVISION RECEIVERS 未知
公开(公告)号：CA2134812A1
公开(公告)日：1995-05-03
申请号：CA2134812
申请日：1994-11-01
申请人： GOVE ROBERT J , MEYER RICHARD C , REDER JOHN R , HEIMBUCH SCOTT D
发明人： GOVE ROBERT J , MEYER RICHARD C , REDER JOHN R , HEIMBUCH SCOTT D
IPC分类号： H04N5/44 , H04N5/445 , H04N5/74 , H04N21/488
摘要： 21 GRAPHICS SUB-DISPLAYS FOR DIGITAL TELEVISION RECEIVERS A graphics data unit (17) for a digital television receiver (10) that uses a spatial light modulator (16). The graphics data unit (17) has a graphics processor (22), which offloads graphics processing tasks, such as for closed captioning and on-screen display, from a main processor (14). The graphics data unit (17) also has a character memory (24), which stores fonts for closed caption and on-screen display characters. A read-only memory (22a) stores graphics primitives. The character fonts and the graphics primitives may be adapted to compensate for staggered pixel layouts of the spatial light modulator (16).

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