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1. 发明专利

DE102006048846B4 Eichschaltung und dieselbe enthaltende Halbleitervorrichtung 未知
公开(公告)号：DE102006048846B4
公开(公告)日：2011-04-28
申请号：DE102006048846
申请日：2006-10-16
申请人： ELPIDA MEMORY INC
发明人： FUJISAWA HIROKI , YOKO HIDEYUKI
IPC分类号： H04L25/12 , G11C7/10 , G11C11/401 , G11C11/4093 , H03K19/0175

2. 发明专利

DE102006048846A1 未知
公开(公告)号：DE102006048846A1
公开(公告)日：2007-09-13
申请号：DE102006048846
申请日：2006-10-16
申请人： ELPIDA MEMORY INC
发明人： FUJISAWA HIROKI , YOKO HIDEYUKI
IPC分类号： H04L25/12 , G11C7/10 , G11C11/401 , G11C11/4093 , H03K19/0175

3. 发明专利

DE102006050103A1 未知
公开(公告)号：DE102006050103A1
公开(公告)日：2007-06-21
申请号：DE102006050103
申请日：2006-10-24
申请人： ELPIDA MEMORY INC
发明人： NAKAMURA MASAYUKI , YOKO HIDEYUKI
IPC分类号： G11C7/10 , H04L25/12 , H03K19/0175
摘要： A ZQ calibration command is internally generated from an external command different from a ZQ calibration command so as to automatically perform an additional ZQ calibration operation. A command interval between an inputted command and a next command is effectively employed to obtain a ZQ calibration period. The external command different from the ZQ calibration command is preferably a self-refreshed command. The addition of the ZQ calibration operation shortens intervals between ZQ calibration operations. Thus, it is possible to obtain a ZQ calibration circuit capable of performing a ZQ calibration operation more accurately.

4. 发明专利

JP2012209497A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012209497A
公开(公告)日：2012-10-25
申请号：JP2011075402
申请日：2011-03-30
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： SHIGESANE YASUYUKI , YOKO HIDEYUKI , IDE AKIRA
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L23/481 , G11C5/025 , G11C5/063 , H01L24/13 , H01L24/14 , H01L25/0657 , H01L2224/0401 , H01L2224/05567 , H01L2224/13009 , H01L2224/13021 , H01L2224/13025 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/13155 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/13091 , H01L2924/15311 , H01L2924/01047 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To stabilize a power supply voltage that is supplied to a controlled chip, relating to a stacked semiconductor device that uses a through electrode.SOLUTION: The semiconductor device includes an interposer IP to which a substrate power supply terminal 91V is provided, an interface chip IF where a surface bump FB is provided on one surface, with a rear surface bump BB provided on the other surface, and a core chip CC connected to the interface chip IF. The positions in plan view, viewed along stacking direction of the surface bump FB and the rear surface bump BB, connected to the substrate power supply terminal 91V, being provided to the interface chip IF, as well as a through electrode TSV1 connecting them, agree among others, with an array pitch P2 of the rear surface bumps BB for signal being shorter than an array pitch P1 of them. Since a power supply can be supplied to the core chip from the interposer IP straight, a power supply voltage that is supplied to the core chip can be stabilized.
摘要翻译：要解决的问题：为了稳定提供给受控芯片的电源电压，涉及使用通孔的层叠半导体器件。解决方案：半导体器件包括设置有基板电源端子91V的插入器IP，在一个表面上设置表面凸块FB的接口芯片IF，在另一个表面上设置有后表面凸块BB，和连接到接口芯片IF的核心芯片CC。连接到基板电源端子91V的连接到基板电源端子91V的表面凸块FB和后表面凸块BB的堆叠方向的平面图中的位置被设置到接口芯片IF，以及连接它们的贯通电极TSV1一致其中，具有用于信号的后表面凸块BB的阵列间距P2比它们的阵列间距P1短。由于可以从插入器IP直线向核心芯片提供电源，所以提供给芯片的电源电压可以稳定。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2011081886A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2011081886A
公开(公告)日：2011-04-21
申请号：JP2009235487
申请日：2009-10-09
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： YOKO HIDEYUKI
IPC分类号： G11C5/00 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H03K19/018521 , G11C5/02 , G11C5/063 , H01L2224/16145 , H01L2924/01037 , H01L2924/01055 , H01L2924/15311 , H04L25/028 , H04L25/0292
摘要： PROBLEM TO BE SOLVED: To suppress a delay in the transmission of a signal in a laminated semiconductor device where a plurality of through-electrodes can selectively be used. SOLUTION: One interface chip IF is electrically connected with a plurality of core chips CC0 to CC7 via the plurality of through-electrodes. A data signal of a driver circuit 401 is inputted to the core chip CC7 via any of the through-electrode 301 or 302. An output switch circuit 190 selects a through-electrode by activating a try state inverter IVR1 or IVR2. The try state inverter amplifies the data signal and sends it to the through-electrode. Similarly, an input switch circuit 192 activates the try state inverter IVT1 or IVT2. The try state inverters also amplifies the data signal sent from the through-electrode and supplies it to a receiver circuit 411. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了抑制可以选择性地使用多个通孔的层叠半导体器件中的信号的传输延迟。解决方案：一个接口芯片IF经由多个通孔与多个芯片CC0至CC7电连接。驱动电路401的数据信号经由贯通电极301或302中的任一个被输入到芯片CC7。输出开关电路190通过激活试用状态转换器IVR1或IVR2来选择通孔。试用状态反相器放大数据信号并将其发送到通孔。类似地，输入开关电路192激活试用状态反相器IVT1或IVT2。试用状态反相器还放大从通孔发送的数据信号并将其提供给接收器电路411.版权所有：（C）2011，JPO＆INPIT

6. 发明专利

JP2008135925A Calibration circuit 有权
标题翻译：校准电路
公开(公告)号：JP2008135925A
公开(公告)日：2008-06-12
申请号：JP2006319937
申请日：2006-11-28
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： YOKO HIDEYUKI
IPC分类号： H03K19/0175 , H01L21/822 , H01L27/04 , H03K19/0948
CPC分类号： G01R31/31713 , G11C29/02 , G11C29/022 , G11C29/028
摘要： PROBLEM TO BE SOLVED: To provide a calibration circuit which is capable of carrying out sufficient calibration operation even in the case where the frequency of an external clock is high. SOLUTION: The calibration circuit comprises: a first replica buffer 110 including the substantially same circuit configuration as a pull-up circuit constituting an output buffer; and a second replica buffer 130 including the substantially same circuit configuration as a pull-down circuit constituting the output buffer. When a first calibration command ZQCS is issued, both of control signals ACT1, ACT2 are activated to simultaneously perform calibration operations on the first and second replica buffers 110, 130. When a second calibration command ZQCL is issued, the control signals ACT1, ACT2 are alternately activated to alternately perform calibration operations on the first and second replica buffers 110, 130. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使在外部时钟的频率高的情况下，也能够提供能够执行足够的校准操作的校准电路。校准电路包括：第一复制缓冲器110，其包括与组成输出缓冲器的上拉电路基本相同的电路配置; 以及第二复制缓冲器130，其包括与组成输出缓冲器的下拉电路基本相同的电路配置。当发出第一校准命令ZQCS时，激活控制信号ACT1，ACT2同时对第一和第二复制缓冲器110,130执行校准操作。当发出第二校准命令ZQCL时，控制信号ACT1，ACT2为交替地激活以在第一和第二复制缓冲器110,130上交替执行校准操作。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2013197576A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013197576A
公开(公告)日：2013-09-30
申请号：JP2012066750
申请日：2012-03-23
申请人： Elpida Memory Inc , エルピーダメモリ株式会社 , Hitachi Ulsi Systems Co Ltd , 株式会社日立超エル・エス・アイ・システムズ
发明人： YOKO HIDEYUKI , ISHIMATSU MANABU , OGAWA NAOKI
IPC分类号： H01L21/66
CPC分类号： G01R31/3187 , G11C5/025 , G11C5/063 , G11C29/1201
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a crack test circuit which can detect whether cracks are generated on a through electrode formation region.SOLUTION: A semiconductor device comprises: a plurality of through electrodes TSV provided in a through electrode formation region; testing wiring 201 provided on the through electrode formation region; a charge circuit 202 for supplying power supply potential VDD to one end 201a of the testing wiring 201; a reset circuit 203 for supplying ground potential VSS to another end 201b of the testing wiring 201; and a determination circuit 204 for determining potential of the other end 201b of the testing wiring 201. Accordingly, whether cracks are generated in an insulation layer and a wiring layer in a region near the plurality of through electrodes TSV can be detected.
摘要翻译：要解决的问题：提供一种具有裂纹测试电路的半导体器件，其可以检测是否在通孔形成区域产生裂纹。解决方案：一种半导体器件包括：设置在贯通电极形成区域中的多个贯通电极TSV; 设置在贯通电极形成区域的测试布线201; 用于向测试布线201的一端201a提供电源电位VDD的充电电路202; 用于将接地电位VSS提供给测试布线201的另一端201b的复位电路203; 以及用于确定测试布线201的另一端201b的电位的确定电路204.因此，可以检测绝缘层中是否产生裂纹，并且可以检测在多个贯通电极TSV附近的区域中的布线层。

8. 发明专利

JP2012175416A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012175416A
公开(公告)日：2012-09-10
申请号：JP2011035683
申请日：2011-02-22
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： YOKO HIDEYUKI , EGUCHI TAKANORI , ISHIMATSU MANABU
IPC分类号： H03K19/0175
CPC分类号： G11C29/022 , G11C29/028
摘要： PROBLEM TO BE SOLVED: To improve a reference potential generating circuit for use in a calibration circuit.SOLUTION: A semiconductor device comprises: a replica buffer 110 driving a calibration terminal ZQ; a reference potential generating circuit 200 generating a reference potential VREF; a comparator circuit 151 comparing a potential appearing at the calibration terminal ZQ with the reference potential VREF; and a control circuit 140 changing the output impedance of the replica buffer 110 based on the comparison result by the comparator circuit 151. The reference potential generating circuit 200 includes a potential generating section 210 activated in response to an enable signal EN and a potential generating section 220 activated regardless of the enable signal EN, and an output node of the potential generating section 210 and an output node of the potential generating section 220 are commonly connected to the comparator circuit 151. For this reason, the reference potential VREF can be correctly output before the enable signal EN is activated.
摘要翻译：要解决的问题：改进用于校准电路的参考电位产生电路。解决方案：半导体器件包括：驱动校准端子ZQ的复制缓冲器110; 产生参考电位VREF的参考电位产生电路200; 将校准端子ZQ出现的电位与参考电位VREF进行比较的比较器电路151; 以及基于比较电路151的比较结果来改变复制缓冲器110的输出阻抗的控制电路140.参考电位产生电路200包括响应于使能信号EN而激活的电位产生部分210和电位产生部分 220被激活，而不管使能信号EN如何，电位产生部分210的输出节点和电位产生部分220的输出节点共同连接到比较器电路151.为此，可以正确地输出参考电位VREF 在使能信号EN被激活之前。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2011082449A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011082449A
公开(公告)日：2011-04-21
申请号：JP2009235490
申请日：2009-10-09
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： YOKO HIDEYUKI , SHIBATA KAYOKO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L27/10897 , G11C5/04 , G11C5/063 , G11C29/12 , H01L22/22 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596
摘要： PROBLEM TO BE SOLVED: To properly maintain receiving-side signal quality, even when an external terminal for test is provided at a signal-receiving side in a stacked semiconductor device capable of selectively utilizing a plurality of through-electrodes. SOLUTION: One interface chip IF and a plurality of core chips CC0-CC7 are stacked, and the semiconductor chips are electrically connected by a plurality of through-electrodes. Data signal of a driver circuit 401 is inputted to the core chip CC7 via either of the through-electrodes 301 and 302. An output selector circuit 184 selects the through-electrode, by activating any of tristate inverters TI1 and IVR2. When a primary selector circuit 186 is to activate the inverter IVS, a test signal is supplied from a test pad TP to a receiver circuit 411. When the inverter IVS is to be activated, a data signal is supplied from any one of through-electrodes to the receiver circuit 411. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使在能够选择性地利用多个通孔的层叠半导体器件中的信号接收侧设置用于测试的外部端子的情况下，为了适当地维持接收侧的信号质量。解决方案：一个接口芯片IF和多个核心芯片CC0-CC7被堆叠，并且半导体芯片通过多个通孔电连接。驱动电路401的数据信号通过贯通电极301,302中的任一个输入到芯片CC7。输出选择电路184通过激活三态逆变器TI1，IVR2中的任意一个来选择贯通电极。当主选择器电路186启动反相器IVS时，测试信号从测试焊盘TP提供给接收器电路411.当反相器IVS被激活时，数据信号从任一个通电极到接收机电路411.版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2013085126A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013085126A
公开(公告)日：2013-05-09
申请号：JP2011223741
申请日：2011-10-11
申请人： Elpida Memory Inc , エルピーダメモリ株式会社 , Hitachi Ulsi Systems Co Ltd , 株式会社日立超エル・エス・アイ・システムズ
发明人： YOKO HIDEYUKI , KAMIMURA KOJI , ISHIMATSU MANABU
IPC分类号： H03K19/0175 , H03K19/0944
CPC分类号： G11C11/4076 , G11C5/147 , G11C11/4093 , G11C29/022 , G11C29/028 , G11C2207/2254 , H03K17/167 , H03K19/0005 , H03K19/018571
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that implements improved precision of impedance adjustment to an output circuit.SOLUTION: The semiconductor device includes: an output circuit (101) including a plurality of unit buffer circuits each having an adjustable impedance; a control circuit (150) for selectively activating one or more of the plurality of unit buffer circuits; and an impedance adjustment section (130) for adjusting the impedance of each of the plurality of unit buffer circuits which includes a replica circuit (131e) having substantially the same adjustable impedance as one of the plurality of unit buffer circuits, and a load current generation circuit (131f) connected in parallel with the replica circuit to change an amount of current flowing through itself in accordance with the number of the one or more unit buffer circuits selectively activated by the control circuit.
摘要翻译：要解决的问题：提供一种对输出电路实现改进的阻抗调整精度的半导体器件。解决方案：半导体器件包括：输出电路（101），包括多个具有可调阻抗的单元缓冲电路; 用于选择性地激活所述多个单元缓冲电路中的一个或多个的控制电路（150）以及阻抗调整部（130），用于调整多个单位缓冲电路中的每一个的阻抗，所述阻抗调整部包括具有与所述多个单位缓冲电路中的一个基本相同的可调阻抗的复制电路（131e）和负载电流产生电路（131f）与复制电路并联连接，以根据由控制电路选择性地激活的一个或多个单元缓冲电路的数量改变流过其自身的电流量。版权所有（C）2013，JPO＆INPIT

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