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1. 发明专利

DE102006051154A1 Semiconductor memory device e.g. dynamic random access memory device, has bit lines forming set of bit line pairs, where lines in one pair are rotated at center between pair of transfer gates on opposite sides of sense amplifier section 未知
公开(公告)号：DE102006051154A1
公开(公告)日：2007-05-24
申请号：DE102006051154
申请日：2006-10-30
申请人： ELPIDA MEMORY INC
发明人： NOBUTOKI TOMOKO , OTA KEN
IPC分类号： G11C7/06 , G11C5/06
摘要： The device has a divided sense amplifier section (SA), and a pair of memory cell arrays (MA-L, MA-R) arranged on opposite sides of the amplifier section. A pair of transfer gates (TG-L, TG-R) is arranged on the opposite sides of the amplifier section and between the cell arrays and the amplifier section. Bit lines (D, DB) form a set of bit line pairs and connect the pair of cell arrays with one another by the transfer gates and the amplifier section. The bit lines in one of the bit line pairs are rotated at the center between the transfer gates on the opposite sides of the amplifier section. An independent claim is also included for a divided sense amplifier section for use in a semiconductor memory device.

2. 发明专利

DE69915158T2 未知
公开(公告)号：DE69915158T2
公开(公告)日：2005-04-07
申请号：DE69915158
申请日：1999-04-22
申请人： ELPIDA MEMORY INC
发明人： NOBUTOKI TOMOKO , MINE KOUJI
IPC分类号： G11C11/41 , G11C5/02 , G11C5/06 , G11C8/10 , G11C11/401 , H01L27/10 , G11C8/00
摘要： It is an object of the invention to provide a semiconductor memory device with a reduced access time by devising a layout of a circuit without elaborate modification. A Y address buffer is situated on the side of an address pad array (the right side), and outputs a signal for controlling Y address decoder situated on the right side and a circuit block communicated therewith. The Y address decoders on the right side control the Y addresses of memory cells in the memory cell arrays C and D in case that data are read therefrom or written thereinto. The circuit block communicated with the Y address buffer outputs a signal to the address decoders on the side of a DQ pad array (the left side) in accordance with the signal inputted from the Y address buffer. The Y address decoders on the left side control the Y addresses of the memory cells in the memory cell arrays A and B in accordance with the signal inputted from the circuit block communicated with the Y address buffer. Data amplifiers combined with the memory cell arrays A, B, C and d respectively amplify the data read from the memory cells in the memory cell arrays A, B, C and D. The circuit blocks situated on both the side ends of a semiconductor chip respectively output activation signals for activating the data amplifiers combined with the memory cell arrays A, B, C and D. The data amplifier-activation signals outputted from the circuit blocks on the left side end are respectively inputted to the delay circuits DL1 and DL2.

3. 发明专利

JP2007157212A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2007157212A
公开(公告)日：2007-06-21
申请号：JP2005348643
申请日：2005-12-02
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： NOBUTOKI TOMOKO , NAGATA KYOICHI
IPC分类号： G11C11/4096 , G11C11/4097
CPC分类号： G11C7/18 , G11C7/02 , G11C7/1006 , G11C11/408 , G11C11/4096 , G11C11/4097
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device where a sorting test etc. is performed easily by correcting an address and a data topology internally.
SOLUTION: The semiconductor storage device has plates 111 to 113 accessed by mutually different row addresses, and is provided with sense amplifier columns 201 and 202 between the plates as shown in the figure 3. In the sense amplifier columns, a type where one pair of bit lines are twisted and a type where any pair of bit lines are not twisted are intermixed. When it is known that access is to be performed through an I/O wiring MIODT_1j as the result of address analysis, input/output data is not inverted. When it is known that access is to be performed through an I/O wiring MIODT_1i, the input/output data is not inverted in accessing to the plate 111, but the input/output data is inverted in accessing to the plate 112.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储装置，其中通过在内部校正地址和数据拓扑容易地执行分类测试等。解决方案：半导体存储装置具有由相互不同的行地址访问的板111至113，并且在板之间设置有读出放大器列201和202，如图3所示。在读出放大器列中，一对位线被扭曲，并且任何一对位线不扭曲的类型被混合。当已知通过地址分析结果通过I / O接线MIODT_1j进行访问时，输入/输出数据不会反转。当已知通过I / O布线MIODT_1i进行访问时，输入/输出数据在进入板111时不反转，但输入/输出数据在进入板112时被反转。
版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007122834A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2007122834A
公开(公告)日：2007-05-17
申请号：JP2005316463
申请日：2005-10-31
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： NOBUTOKI TOMOKO , OTA MASARU
IPC分类号： G11C11/401 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C7/02 , G11C5/063 , G11C7/06 , G11C7/1048 , G11C7/1051 , G11C7/18 , G11C11/4091 , G11C11/4093 , G11C11/4097
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device provided with a sense amplifier which is small in area and can reduce inter adjacent bit line noise in the sense amplifier. SOLUTION: In the sense amplifier of the semiconductor memory device, a pair of bit lines are twisted in the sense amplifier positioned at an almost center position between left and right transfer gates. Adjacent coupling noises are canceled by twisting the pair of bit lines of every other group. Thus, the sense amplifier in which the pair of bit lines are twisted without increasing layout area and influence of adjacent coupling noise in the sense amplifier never be affected and which is operated at high speed and stably and the semiconductor memory device provided with this sense amplifier can be obtained. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有面积小的读出放大器的半导体存储器件，并且可以减少读出放大器中相邻的位线噪声。解决方案：在半导体存储器件的读出放大器中，位于左右传输门之间几乎中心位置的读出放大器中的一对位线被扭曲。通过扭转每个其他组的一对位线来消除相邻的耦合噪声。因此，读出放大器中的一对比特线被扭曲而不增加布局面积和感测放大器中相邻耦合噪声的影响，不会受到影响，并且高速且稳定地运行，并且设置有该读出放大器的半导体存储器件可以获得。版权所有（C）2007，JPO＆INPIT

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