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1. 发明授权

US07329941B2 Creating increased mobility in a bipolar device 失效
标题翻译：在双极设备中增加移动性
公开(公告)号：US07329941B2
公开(公告)日：2008-02-12
申请号：US10710548
申请日：2004-07-20
申请人： Dureseti Chidambarrao , Gregory G. Freeman , Marwan H. Khater
发明人： Dureseti Chidambarrao , Gregory G. Freeman , Marwan H. Khater
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by applying a stress film adjacent an emitter structure of the device and atop a base film of the device. In this manner, the compressive and tensile strain are located in close proximity to an intrinsic portion of the device. A suitable material for the stress film is nitride. The emitter structure may be “T-shaped”, having a lateral portion atop an upright portion, a bottom of the upright portion forms a contact to the base film, and the lateral portion overhangs the base film.
摘要翻译：双极（BJT）器件中的载流子的迁移率通过在器件中产生压缩应变以增加器件中电子的迁移率而增加，并且在器件中产生拉伸应变以增加器件中的孔的移动性。通过在装置的发射极结构附近施加应力膜并且在器件的基底上方施加应力膜来产生压缩和拉伸应变。以这种方式，压缩和拉伸应变位于设备本身部分附近。适用于应力膜的材料是氮化物。发射体结构可以是“T形”，其具有在直立部分顶部的侧面部分，直立部分的底部形成与基底膜的接触，并且侧向部分悬垂在基底膜上。

2. 发明授权

US07741186B2 Creating increased mobility in a bipolar device 失效
标题翻译：在双极设备中增加移动性
公开(公告)号：US07741186B2
公开(公告)日：2010-06-22
申请号：US11946940
申请日：2007-11-29
申请人： Dureseti Chidambarrao , Gregory G. Freeman , Marwan H. Khater
发明人： Dureseti Chidambarrao , Gregory G. Freeman , Marwan H. Khater
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by applying a stress film adjacent an emitter structure of the device and atop a base film of the device. In this manner, the compressive and tensile strain are located in close proximity to an intrinsic portion of the device. A suitable material for the stress film is nitride. The emitter structure may be “T-shaped”, having a lateral portion atop an upright portion, a bottom of the upright portion forms a contact to the base film, and the lateral portion overhangs the base film.
摘要翻译：双极（BJT）器件中的载流子的迁移率通过在器件中产生压缩应变以增加器件中电子的迁移率而增加，并且在器件中产生拉伸应变以增加器件中的孔的移动性。通过在装置的发射极结构附近施加应力膜并且在器件的基底上方施加应力膜来产生压缩和拉伸应变。以这种方式，压缩和拉伸应变位于设备本身部分附近。适用于应力膜的材料是氮化物。发射体结构可以是“T形”，其具有在直立部分顶部的侧面部分，直立部分的底部形成与基底膜的接触，并且侧向部分悬垂在基底膜上。

3. 发明授权

US07102205B2 Bipolar transistor with extrinsic stress layer 有权
标题翻译：具有外应力层的双极晶体管
公开(公告)号：US07102205B2
公开(公告)日：2006-09-05
申请号：US10931660
申请日：2004-09-01
申请人： Dureseti Chidambarrao , Gregory G. Freeman , Marwan H. Khater
发明人： Dureseti Chidambarrao , Gregory G. Freeman , Marwan H. Khater
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/242 , H01L29/7378
摘要： A method of increasing mobility of charge carriers in a bipolar device comprises the steps of: creating compressive strain in the device to increase mobility of holes in an intrinsic base of the device; and creating tensile strain in the device to increase mobility of electrons in the intrinsic base of the device. The compressive and tensile strains are created by forming a stress layer in close proximity to the intrinsic base of the device. The stress layer is at least partially embedded in a base layer of the device, adjacent an emitter structure of the device. The stress layer has different lattice constant than the intrinsic base. Method and apparatus are described.
摘要翻译：增加双极器件中电荷载流子迁移率的方法包括以下步骤：在器件中产生压缩应变以增加器件的本征基极中的孔的迁移率; 并且在器件中产生拉伸应变以增加器件本征基底中电子的迁移率。压缩和拉伸应变是通过在紧邻该装置的固有基底的位置形成应力层来产生的。应力层至少部分地嵌入在器件的基底层中，与器件的发射极结构相邻。应力层具有与内在基体不同的晶格常数。描述了方法和装置。

4. 发明申请

US20090079026A1 STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：半导体绝缘体器件的应力发生结构
公开(公告)号：US20090079026A1
公开(公告)日：2009-03-26
申请号：US11860851
申请日：2007-09-25
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

5. 发明授权

US08629501B2 Stress-generating structure for semiconductor-on-insulator devices 有权
标题翻译：绝缘体上半导体器件的应力产生结构
公开(公告)号：US08629501B2
公开(公告)日：2014-01-14
申请号：US13370898
申请日：2012-02-10
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L27/12
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

6. 发明申请

US20120139081A1 STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
标题翻译：半导体绝缘体器件的应力发生结构
公开(公告)号：US20120139081A1
公开(公告)日：2012-06-07
申请号：US13370898
申请日：2012-02-10
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

7. 发明授权

US08115254B2 Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same 有权
标题翻译：绝缘体上半导体结构，包括含有绝缘体应力插头的沟槽及其制造方法
公开(公告)号：US08115254B2
公开(公告)日：2012-02-14
申请号：US11860851
申请日：2007-09-25
申请人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
发明人： Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
IPC分类号： H01L27/12
CPC分类号： H01L29/0603 , H01L21/76224 , H01L29/1025 , H01L29/1054 , H01L29/84
摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
摘要翻译：在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。氧化硅材料沉积在深沟槽中，平坦化和凹陷。去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

8. 发明授权

US09059316B2 Structure and method for mobility enhanced MOSFETs with unalloyed silicide 有权
标题翻译：具有非合金化硅化物的迁移率增强型MOSFET的结构和方法
公开(公告)号：US09059316B2
公开(公告)日：2015-06-16
申请号：US13397860
申请日：2012-02-16
申请人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
发明人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
IPC分类号： H01L21/8238 , H01L21/768 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/78 , H01L27/32 , H01L29/165
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
摘要翻译：虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

9. 发明授权

US08871576B2 Silicon nanotube MOSFET 有权
标题翻译：硅纳米管MOSFET
公开(公告)号：US08871576B2
公开(公告)日：2014-10-28
申请号：US13036292
申请日：2011-02-28
申请人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
发明人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
IPC分类号： H01L29/49 , H01L29/06 , B82Y10/00 , H01L29/775 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78 , B82Y10/00 , H01L29/0676 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates. The method of forming the nanotubular MOSFET device includes: forming on a substrate a cylindrical shaped Si layer; forming an outer gate surrounding the cylindrical Si layer and positioned between a bottom spacer and a top spacer; growing a silicon epitaxial layer on the top spacer adjacent to a portion of the cylindrical shaped Si layer; etching an inner portion of the cylindrical shaped Si forming a hollow cylinder; forming an inner spacer at the bottom of the inner cylinder; forming an inner gate by filling a portion of the hollow cylinder; forming a sidewall spacer adjacent to the inner gate; and etching a deep trench for accessing and contacting the outer gate and drain.
摘要翻译：纳米管MOSFET器件及其制造方法用于扩展器件缩放路线图，同时保持良好的短沟道效应并提供有竞争力的驱动电流。纳米管MOSFET器件包括通过管状外延生长硅层彼此分离的同心管状内部和外部栅极，以及分别由围绕管状内部和外部门的间隔开的源极和漏极。形成纳米管MOSFET器件的方法包括：在衬底上形成圆柱形的Si层; 形成围绕圆柱形Si层并位于底部间隔件和顶部间隔件之间的外部门; 在与圆柱形Si层的一部分相邻的顶部间隔上生长硅外延层; 蚀刻形成中空圆筒的圆柱形Si的内部; 在内筒的底部形成内隔板; 通过填充中空圆筒的一部分形成内门; 形成邻近所述内门的侧壁间隔物; 并蚀刻用于访问和接触外部栅极和漏极的深沟槽。

10. 发明授权

US08803243B2 Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor 有权
标题翻译：具有通过金属栅极导体连接的栅极结构的互补金属氧化物半导体（CMOS）器件
公开(公告)号：US08803243B2
公开(公告)日：2014-08-12
申请号：US13342435
申请日：2012-01-03
申请人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
发明人： Yue Liang , Dureseti Chidambarrao , Brian J. Greene , William K. Henson , Unoh Kwon , Shreesh Narasimha , Xiaojun Yu
IPC分类号： H01L21/70
CPC分类号： H01L21/823871 , H01L21/28079 , H01L21/30604 , H01L21/76224 , H01L21/823878 , H01L29/4958
摘要： A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
摘要翻译：一种互补金属氧化物半导体（CMOS）器件，包括包括第一有源区和第二有源区的衬底，其中衬底的第一有源区和第二有源区中的每一个被隔离区彼此分开。 n型半导体器件存在于衬底的第一有源区上，其中n型半导体器件包括栅极结构的第一部分。 p型半导体器件存在于衬底的第二有源区上，其中p型半导体器件包括栅极结构的第二部分。连接栅极部分提供栅极结构的第一部分和栅极结构的第二部分之间的电连接。与连接栅极部分的电接触超过隔离区域，并且不在第一有源区域和/或第二有源区域之上。

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