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1. 发明授权

US07325221B1 Logic system with configurable interface 有权
标题翻译：具有可配置接口的逻辑系统
公开(公告)号：US07325221B1
公开(公告)日：2008-01-29
申请号：US09634045
申请日：2000-08-08
申请人： Drew Eric Wingard , Michael J. Meyer , Geert P. Rosseel , Lisa Robinson , Jay Tomlinson
发明人： Drew Eric Wingard , Michael J. Meyer , Geert P. Rosseel , Lisa Robinson , Jay Tomlinson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/66
摘要： A core block with a highly configurable interface such that the interface of the core can be optimally configured for the system the core is integrated into. In one embodiment the method consists of defining a configurable interface with different configuration options, capturing the specific core configuration through manual entry or through the use of a Graphical User Interface, and providing for software that combines the source description of the core with the configuration data to generate the core with an optimally configured logic and circuit interface.
摘要翻译：具有高度可配置接口的核心块，使得核心的接口可以被最佳地配置为集成到核心的系统。在一个实施例中，该方法包括定义具有不同配置选项的可配置接口，通过手动输入或通过使用图形用户界面来捕获特定的核心配置，以及提供将核心的源描述与配置数据组合的软件以最佳配置的逻辑和电路接口生成核心。

2. 发明授权

US07165094B2 Communications system and method with non-blocking shared interface 有权
标题翻译：具有非阻塞共享接口的通信系统和方法
公开(公告)号：US07165094B2
公开(公告)日：2007-01-16
申请号：US09802405
申请日：2001-03-09
申请人： Wolf-Dietrich Weber , Richard Aras , Lisa A. Robinson , Geert P. Rosseel , Jay S. Tomlinson , Drew E. Wingard
发明人： Wolf-Dietrich Weber , Richard Aras , Lisa A. Robinson , Geert P. Rosseel , Jay S. Tomlinson , Drew E. Wingard
IPC分类号： G06F15/16
CPC分类号： G06F13/14 , G06F9/54
摘要： A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection. A connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a thread identifier that indicates a transaction stream that the data transfer is part of and a busy signal identified by the thread identifier. The busy signal is issued by the target functional block when resources will be unavailable to perform a transfer.
摘要翻译：通讯系统一个实施例包括至少两个功能块，其中第一功能块通过建立连接与第二功能块通信。连接是数据可以在第一功能块和第二功能块之间通过的逻辑状态。一个实施例包括耦合到每个功能块并被配置为承载多个信号的总线。多个信号包括指示数据传输是其中一部分的事务流的线程标识符和由线程标识符标识的忙信号。当资源不可用时执行传输，目标功能块发出忙信号。

3. 发明授权

US5329187A High speed differential comparator 失效
标题翻译：高速差分比较器
公开(公告)号：US5329187A
公开(公告)日：1994-07-12
申请号：US18619
申请日：1993-02-17
申请人： Finbarr J. Crispie , Geert P. Rosseel
发明人： Finbarr J. Crispie , Geert P. Rosseel
IPC分类号： G01R19/165 , G01R19/00 , H03K5/08 , H03K5/24 , H03K3/02
CPC分类号： H03K5/249 , G01R19/0038
摘要： This invention relates to a capacitive switching network for producing signals of opposite polarity. In one embodiment of the invention, a first signal (V1) is applied to the first plate of a first capacitor (C1) and a second signal (V2) is applied to the first plate of a second capacitor (C2). The first plates of the first and second capacitors are then shorted together to produce a combined voltage (Vc). The generation of Vc causes an AC voltage equal to (Vc-V1) to be produced at the second plate of C1 and an AC voltage equal to (Vc-V2) to be produced at the second plate of C2. By way of example, for C1 equal to C2, there is produced a Vc equal to (V1+V2)/2. Furthermore, if V1 is greater than V2, a negative going AC signal equal to (VC-V1) is produced at the second plate of C1, and a positive going AC signal equal to (Vc-V2) is produced at the second plate of C2. The capacitive network of the invention is highly suited for use in high speed differential comparators.
摘要翻译：本发明涉及用于产生相反极性的信号的电容开关网络。在本发明的一个实施例中，将第一信号（V1）施加到第一电容器（C1）的第一板，并且第二信号（V2）施加到第二电容器（C2）的第一板。然后将第一和第二电容器的第一板短路在一起以产生组合电压（Vc）。 Vc的产生导致在C1的第二板处产生等于（Vc-V1）的AC电压，并且在C2的第二板处产生等于（Vc-V2）的AC电压。作为示例，对于等于C2的C1，产生等于（V1 + V2）/ 2的Vc。此外，如果V1大于V2，则在C1的第二板处产生等于（VC-V1）的负交流信号，并且在第二板处产生等于（Vc-V2）的正向交流信号 C2。本发明的电容网络非常适用于高速差分比较器。

4. 发明授权

US5332931A High speed differential comparator 失效
标题翻译：高速差分比较器
公开(公告)号：US5332931A
公开(公告)日：1994-07-26
申请号：US720082
申请日：1991-06-24
申请人： Finbarr J. Crispie , Geert P. Rosseel
发明人： Finbarr J. Crispie , Geert P. Rosseel
IPC分类号： G01R19/165 , G01R19/00 , H03K5/08 , H03K5/24
CPC分类号： H03K5/249 , G01R19/0038
摘要： A differential comparator with inputs switched and capacitively coupled to inverters which have capacitive cross-coupling feedback for a latching operation. The inverters also have direct switched feedback for autozeroing. The inputs further have a shorting switch between the input switches and the coupling capacitors for offset compensation. Complementary operation of the switches provides precharge and evaluation phases of operation. During precharge the inputs are applied to the input coupling capacitors and the inverters are autozeroed; during evaluation the inputs are transferred to the inverters through the coupling capacitors and the outputs feedback positively through the cross-coupling capacitors to latch the pair of inverters.
摘要翻译：具有输入开关和电容耦合到具有用于锁存操作的电容性交叉耦合反馈的反相器的差分比较器。逆变器还具有用于自动调零的直接开关反馈。输入端还具有输入开关和用于偏移补偿的耦合电容器之间的短路开关。交换机的互补操作提供了预充电和评估阶段的操作。在预充电期间，输入被施加到输入耦合电容器，并且逆变器是自动归零的; 在评估期间，输入通过耦合电容器传输到逆变器，并且输出端通过交叉耦合电容积极反馈以锁存该对逆变器。

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