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1. 发明授权

US5644313A Redundant signed digit A-to-D conversion circuit and method thereof 失效
标题翻译：冗余有符号数字A转D电路及其方法
公开(公告)号：US5644313A
公开(公告)日：1997-07-01
申请号：US463818
申请日：1995-06-05
申请人： Patrick L. Rakers , Douglas A. Garrity
发明人： Patrick L. Rakers , Douglas A. Garrity
IPC分类号： H03M1/06 , H03M1/40
CPC分类号： H03M1/403 , H03M1/0682
摘要： RSD n-bit analog-to-digital converter (10) receives voltage VIN that is compared to reference voltages VH and VL in the first stage (18). A digital code, representing VIN, is generated at first stage outputs (24, 26). First stage residue voltage V22 is compared to VH and VL in the second stage (30). A digital code generated at the outputs (28, 32) of the second stage, represent residue voltage V22. Residue voltage V22 is recycled through the first and second stages. Upon reaching the n.sup.th conversion bit, residue voltage V22 of the n.sup.th -1 bit is compared to second stage mid-level voltage reference VMID. A digital code generated at the outputs of the second stage represents the n.sup.th -1 bit residue voltage V22. The digital codes are stored in storage elements (34) and added in a binary adder (38) to provide the n-bit representation of VIN.
摘要翻译： RSD n位模数转换器（10）接收与第一级（18）中的参考电压VH和VL相比较的电压VIN。代表VIN的数字代码在第一级输出（24,26）产生。将第一级残留电压V22与第二级（30）中的VH和VL进行比较。在第二级的输出端（28,32）产生的数字码表示残留电压V22。残余电压V22通过第一和第二阶段再循环。在到达第n个转换位时，将第n-1位的残余电压V22与第二级中间电平参考VMID进行比较。在第二级的输出处产生的数字代码表示第n位残留电压V22。数字代码被存储在存储元件（34）中并被加到二进制加法器（38）中以提供VIN的n位表示。

2. 发明授权

US5625360A Current source for reducing noise glitches generated in a digital to analog converter and method therefor 失效
标题翻译：用于减少数模转换器中产生的噪声毛刺的电流源及其方法
公开(公告)号：US5625360A
公开(公告)日：1997-04-29
申请号：US524095
申请日：1995-09-05
申请人： Douglas A. Garrity , Patrick L. Rakers
发明人： Douglas A. Garrity , Patrick L. Rakers
IPC分类号： H03M1/08 , H03M1/66 , H03M1/74
CPC分类号： H03M1/0863 , H03M1/662 , H03M1/742
摘要： A switchable current source (41) for a Digital to Analog Converter (DAC) to reduce noise glitches when a change in total current provided by the DAC occurs. The switchable current source (41) is one of many required by a DAC to convert a digital signal to an analog signal. Each current source of the DAC receives an input voltage that enables or disables the current source from providing or not providing a current. A sampled input voltage is alternately provided to the switchable current source (41) by a first flip flop (42) or a second flip flop (43). One flip flop samples the input voltage while the other provides a previous sampled input voltage for enabling and disabling the switchable current source (41). Switches (46,47) couple an output voltage of the first or second flip flops (42,43) a predetermined time after the output voltage changes to a transistor (51) coupled to a current source (53).
摘要翻译：用于数模转换器（DAC）的可切换电流源（41），用于在发生DAC提供的总电流变化时减少噪声毛刺。可切换电流源（41）是DAC将数字信号转换为模拟信号的许多要求之一。 DAC的每个电流源接收输入电压，其使能或禁止当前源提供或不提供电流。通过第一触发器（42）或第二触发器（43）将采样的输入电压交替地提供给可切换电流源（41）。一个触发器对输入电压进行采样，而另一个触发器提供用于启用和禁用可切换电流源（41）的先前采样输入电压。在输出电压改变到耦合到电流源（53）的晶体管（51）之后的预定时间内，开关（46,47）耦合第一或第二触发器（42,43）的输出电压。

3. 发明授权

US5525920A Comparator circuit and method thereof 失效
标题翻译：比较器电路及其方法
公开(公告)号：US5525920A
公开(公告)日：1996-06-11
申请号：US431965
申请日：1995-05-01
申请人： Patrick L. Rakers , Douglas A. Garrity
发明人： Patrick L. Rakers , Douglas A. Garrity
IPC分类号： H03K5/24 , H03K5/22
CPC分类号： H03K5/2472
摘要： Comparator circuit (72) samples a differential input signal at switched capacitor circuit (100). The input signal is stored across capacitors (128, 130, 132, 134). Reference voltages are subtracted from the input signal to produce a difference signal. The difference is compared to a mid-supply reference VMID, and an amplified representation of the signal is produced at the output of differential gain stage (136). Latching output stage (138) uses feedback circuits (204, 211 and 202, 208) to process the amplified signal and to produce a rail to rail representation of the amplified signal at the inputs (146, 148) of SR latch (140). The feedback circuit also powers-down the output stage after processing the amplified signal. Buffer circuits (205, 213 and 214, 212) allow a new signal to be processed by capacitor circuit (100) while the previous signal is being stored in the SR latch.
摘要翻译：比较器电路（72）在开关电容器电路（100）处采样差分输入信号。输入信号存储在电容器（128,130,132,134）之间。从输入信号中减去参考电压以产生差分信号。将差值与中间电源参考VMID进行比较，并且在差分增益级（136）的输出处产生信号的放大表示。锁存输出级（138）使用反馈电路（204,211和202,208）来处理放大的信号并且在SR锁存器（140）的输入端（146,148）处产生放大信号的轨至轨表示。反馈电路在处理放大信号之后还对输出级进行掉电。当先前的信号被存储在SR锁存器中时，缓冲电路（205,213和214,212）允许由电容器电路（100）处理新的信号。

4. 发明授权

US5894284A Common-mode output sensing circuit 失效
标题翻译：共模输出检测电路
公开(公告)号：US5894284A
公开(公告)日：1999-04-13
申请号：US753812
申请日：1996-12-02
申请人： Douglas A. Garrity , Patrick L. Rakers
发明人： Douglas A. Garrity , Patrick L. Rakers
IPC分类号： H03F3/00 , H03F3/45 , H03M1/44
CPC分类号： H03F3/005 , H03F3/45479 , H03M1/442
摘要： A common-mode sensing circuit (504) of a clocked differential amplifier (602) includes a refresh circuit (604) which precharges a capacitance during a first clock phase (P.sub.1) and discharges the capacitance to drive the outputs (514, 516) of the differential amplifier (602) to a desired common-mode voltage (V.sub.AGO) during a second clock phase, which increases the output loading during the second clock phase (P.sub.2). A load balancing circuit (606) selectively switches a load to the outputs (514, 516) during the first clock phase (P.sub.1) to match the load produced by the refresh circuit (604) during the second clock phase (P.sub.2).
摘要翻译：时钟差分放大器（602）的共模感测电路（504）包括刷新电路（604），其在第一时钟相位（P1）期间对电容进行预充电，并且将电容放电以驱动输出（514,516）的差分放大器（602）在第二时钟相位期间达到期望的共模电压（VAGO），这增加了在第二时钟相位（P2）期间的输出负载。负载平衡电路（606）在第一时钟相位（P1）期间选择性地将负载切换到输出（514,516）以匹配在第二时钟相位（P2）期间由刷新电路（604）产生的负载。

5. 发明授权

US5818276A Non-overlapping clock generator circuit and method therefor 失效
标题翻译：非重叠时钟发生器电路及其方法
公开(公告)号：US5818276A
公开(公告)日：1998-10-06
申请号：US610178
申请日：1996-03-04
申请人： Douglas A. Garrity , Patrick L. Rakers , Andrea Eberhardt
发明人： Douglas A. Garrity , Patrick L. Rakers , Andrea Eberhardt
IPC分类号： H03K5/151 , H03H11/16
CPC分类号： H03K5/1515
摘要： A non-inverting, inverting, delayed non-inverting, and delayed inverting non-overlapping clock signal is provided by a non-overlapping clock generator circuit (41, 61). The non-overlapping clock generator circuit (41, 61) increases time for circuit operation by minimizing delays between non-overlapping clock signals and simultaneously transitioning rising edges of clock signals. A non-overlapping clock generation circuit (41) comprises six NOR gates (43-48) and an inverter (42). Three NOR gates form a first delay line (43-45) and the remaining three NOR gates form a second delay line (46-48). The inverter (42) provides an inverted clock signal to the second delay line. A clock signal propagates through one delay line while the other delay line is non-responsive due to a feedback signal from the active delay line. Once the clock signal has propagated through the active delay line, the feedback signal changes and allows NOR gates of the remaining delay line to simultaneously provide a clock signal and a delayed clock signal.
摘要翻译：由非重叠时钟发生器电路（41,61）提供非反相，反相，延迟的非反相和延迟的反相非重叠时钟信号。不重叠的时钟发生器电路（41,61）通过最小化不重叠的时钟信号之间的延迟并同时转换时钟信号的上升沿来增加电路操作的时间。非重叠时钟产生电路（41）包括六个或非门（43-48）和一个反相器（42）。三个或非门形成第一延迟线（43-45），其余三个或非门形成第二延迟线（46-48）。反相器（42）向第二延迟线提供反相时钟信号。时钟信号通过一个延迟线传播，而另一个延迟线由于来自有源延迟线的反馈信号而不响应。一旦时钟信号已经通过有源延迟线传播，反馈信号改变并允许剩余延迟线的“或非”门同时提供时钟信号和延迟的时钟信号。

6. 发明授权

US5574457A Switched capacitor gain stage 失效
标题翻译：开关电容器增益级
公开(公告)号：US5574457A
公开(公告)日：1996-11-12
申请号：US489349
申请日：1995-06-12
申请人： Douglas A. Garrity , Patrick L. Rakers
发明人： Douglas A. Garrity , Patrick L. Rakers
IPC分类号： H03F3/00 , H03F3/70 , H03H19/00 , H03M1/44 , H03M1/12
CPC分类号： H03M1/442 , H03F3/005 , H03H19/004
摘要： A switched capacitor gain stage (21) that samples an input voltage every clock cycle phase for effectively doubling the frequency of operation. The switched capacitor gain stage (21) comprising an amplifier (22), a first capacitor network, and a second capacitor network. Either the first or second capacitor network is sampling an input voltage. For example, the first capacitor network samples an input voltage. Capacitors of the first capacitor network are coupled to sample the input voltage via switches. Capacitors of the second switched capacitor network are coupled around the amplifier (22) in a gain configuration via switches. The capacitors of the second switched capacitor network having a voltage stored from a previous clock phase. In a next clock phase the second switched capacitor network are coupled via switches for sampling an input voltage and the first switched capacitor network is coupled via switches in a gain configuration around the amplifier (22).
摘要翻译：开关电容器增益级（21），每个时钟周期阶段对输入电压进行采样，以有效地加倍工作频率。开关电容器增益级（21）包括放大器（22），第一电容器网络和第二电容器网络。第一或第二电容器网络都要对输入电压进行采样。例如，第一电容器网络对输入电压进行采样。第一电容器网络的电容器被耦合以通过开关对输入电压进行采样。第二开关电容器网络的电容器通过开关以增益配置耦合在放大器（22）周围。第二开关电容器网络的电容器具有从先前时钟相位存储的电压。在下一个时钟阶段，第二开关电容器网络通过用于对输入电压进行采样的开关耦合，并且第一开关电容器网络通过放大器（22）周围的增益配置的开关耦合。

7. 发明申请

US20130314271A1 VEHICLE-BORNE RADAR SYSTEMS WITH CONTINUOUS-TIME, SIGMA DELTA ANALOG-TO-DIGITAL CONVERTERS, AND METHODS OF THEIR OPERATION 审中-公开
标题翻译：具有连续时间的车载雷达雷达系统，SIGMA DELTA模拟数字转换器及其操作方法
公开(公告)号：US20130314271A1
公开(公告)日：2013-11-28
申请号：US13480977
申请日：2012-05-25
申请人： Brandt Braswell , Douglas A. Garrity , Mohammad Nizam U. Kabir
发明人： Brandt Braswell , Douglas A. Garrity , Mohammad Nizam U. Kabir
IPC分类号： G01S13/93 , G01S13/00 , G01S13/08
CPC分类号： G01S13/34 , G01S7/352 , G01S13/931 , G01S2013/9314 , G01S2013/9321 , G01S2013/9325 , G01S2013/9332 , G01S2013/9342 , G01S2013/9346 , G01S2013/9375 , G01S2013/9378 , G01S2013/9385 , H03M3/424 , H03M3/448 , H03M3/452 , H03M3/454
摘要： Embodiments of vehicle-borne radar systems and methods of their operation are provided. The vehicle-borne radar system includes a transmit path and a first receive path. The transmit path is capable of producing a signal for transmission over an air interface (e.g., a frequency modulated continuous wave (FMCW) signal). The receive path includes a continuous-time (CT) sigma delta analog-to-digital converter (ADC), and the receive path is capable of receiving a reflected version of the signal from the air interface, and converting the reflected version along the receive path into a sequence of digital samples using the CT sigma delta ADC. In an embodiment, the transmit path and the receive path are integrated onto a single integrated circuit.
摘要翻译：提供车载雷达系统的实施例及其操作方法。车载雷达系统包括发射路径和第一接收路径。发射路径能够产生用于通过空中接口传输的信号（例如，调频连续波（FMCW）信号）。接收路径包括连续时间（CT）Σ-Δ模数转换器（ADC），并且接收路径能够从空中接口接收信号的反射版本，并沿接收器转换反射版本使用CT西格玛Delta ADC的数字采样序列。在一个实施例中，发射路径和接收路径被集成到单个集成电路上。

8. 发明申请

US20130187805A1 PIPELINED ANALOG-TO-DIGITAL CONVERTER HAVING REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的管道模拟数字转换器
公开(公告)号：US20130187805A1
公开(公告)日：2013-07-25
申请号：US13355657
申请日：2012-01-23
申请人： Douglas A. Garrity
发明人： Douglas A. Garrity
IPC分类号： H03M1/12
CPC分类号： H03M1/1215 , H03M1/1245
摘要： A pipelined analog-to-digital converter is provided that has advantages of both a high input sample rate as well as low power consumption due to having all but the first pipeline stage operate at a frequency that is a fraction of the input sample rate. The first stage of the pipelined ADC has an internal operating frequency that is the full ADC sample rate, and samples the input signal on the same clock edge for each sample. Subsequent pipeline stages have parallel input sampling circuitry that samples provided input signals at a reduced rate. Since the input sampling circuitry operates at a reduced frequency, power consumption is reduced by those stages. Further, by virtue of sampling the input signal on the same clock edge for each sample, frequency response image generation issues associated with ADC architectures that sample the input signal on more than one clock edge are avoided.
摘要翻译：提供了一种流水线模数转换器，其具有高输入采样率以及低功耗的优点，因为除了第一流水线级之外的所有流水线阶段都以输入采样率的一部分的频率进行操作。流水线ADC的第一级具有内部工作频率，为完整的ADC采样率，并为每个采样在相同时钟边沿采样输入信号。后续流水线级具有并行输入采样电路，以降低的速率对提供的输入信号进行采样。由于输入采样电路以降低的频率运行，因此这些级的功耗降低。此外，通过在每个采样的相同时钟沿对输入信号进行采样，避免了与在多于一个时钟沿上采样输入信号的ADC架构相关的频率响应图像生成问题。

9. 发明授权

US08487803B1 Pipelined analog-to-digital converter having reduced power consumption 有权
标题翻译：流水线模数转换器具有降低的功耗
公开(公告)号：US08487803B1
公开(公告)日：2013-07-16
申请号：US13355657
申请日：2012-01-23
申请人： Douglas A. Garrity
发明人： Douglas A. Garrity
IPC分类号： H03M1/38
CPC分类号： H03M1/1215 , H03M1/1245
摘要： A pipelined analog-to-digital converter is provided that has advantages of both a high input sample rate as well as low power consumption due to having all but the first pipeline stage operate at a frequency that is a fraction of the input sample rate. The first stage of the pipelined ADC has an internal operating frequency that is the full ADC sample rate, and samples the input signal on the same clock edge for each sample. Subsequent pipeline stages have parallel input sampling circuitry that samples provided input signals at a reduced rate. Since the input sampling circuitry operates at a reduced frequency, power consumption is reduced by those stages. Further, by virtue of sampling the input signal on the same clock edge for each sample, frequency response image generation issues associated with ADC architectures that sample the input signal on more than one clock edge are avoided.
摘要翻译：提供了一种流水线模数转换器，其具有高输入采样率以及低功耗的优点，因为除了第一流水线级之外的所有流水线阶段都以输入采样率的一部分的频率进行操作。流水线ADC的第一级具有内部工作频率，为完整的ADC采样率，并为每个采样在相同时钟边沿采样输入信号。后续流水线级具有并行输入采样电路，以降低的速率对提供的输入信号进行采样。由于输入采样电路以降低的频率运行，因此这些级的功耗降低。此外，通过在每个采样的相同时钟沿对输入信号进行采样，避免了与在多于一个时钟沿上采样输入信号的ADC架构相关的频率响应图像生成问题。

10. 发明申请

US20120249237A1 CORRELATED-LEVEL-SHIFTING AND CORRELATED-DOUBLE-SAMPLING SWITCHED-CAPACITOR GAIN STAGES, SYSTEMS IMPLEMENTING THE GAIN STAGES, AND METHODS OF THEIR OPERATION 有权
标题翻译：相关水平和相关双重采样开关电容器增益级别，实现增益级别的系统及其运行方法
公开(公告)号：US20120249237A1
公开(公告)日：2012-10-04
申请号：US13075956
申请日：2011-03-30
申请人： Douglas A. Garrity , Brandt Braswell
发明人： Douglas A. Garrity , Brandt Braswell
IPC分类号： H03G3/20
CPC分类号： H03F3/005 , H03F3/45475 , H03F3/45986 , H03G1/0094
摘要： Embodiments of apparatus and methods for applying a gain to an input signal are provided. An embodiment of a switched-capacitor gain stage circuit includes an input node, an output node, an operational amplifier, a correlated-double-sampling portion, a correlated-level-shifting portion, and a switching configuration. The operational amplifier has a first amplifier input, a second amplifier input, and an amplifier output. The correlated-double-sampling portion includes a plurality of sampling capacitors arranged in parallel and selectively coupled between the input node and a central node, and an offset storage capacitor including a first terminal coupled to the first amplifier input. The correlated-level-shifting portion includes a correlated-level-shifting capacitor including a first terminal coupled to the output node. The switching configuration has multiple switches that are controllable sequentially to place the gain stage circuit in a sampling state, an approximate output voltage storage state, a level shifting and gain state, and an output state.
摘要翻译：提供了用于向输入信号施加增益的装置和方法的实施例。开关电容器增益级电路的实施例包括输入节点，输出节点，运算放大器，相关双采样部分，相关电平转换部分和切换配置。运算放大器具有第一放大器输入，第二放大器输入和放大器输出。相关双采样部分包括并联布置并选择性地耦合在输入节点和中心节点之间的多个采样电容器和包括耦合到第一放大器输入的第一端子的偏移存储电容器。相关电平移位部分包括相关电平移位电容器，其包括耦合到输出节点的第一端子。开关配置具有可以顺序控制的多个开关，以将增益级电路置于采样状态，近似输出电压存储状态，电平移位和增益状态以及输出状态。

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