专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130222216A1 DISPLAY APPARATUS AND METHOD OF DRIVING THE SAME 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US20130222216A1
公开(公告)日：2013-08-29
申请号：US13489980
申请日：2012-06-06
申请人： Dong-Won PARK , Jae Sung BAE , Bonghyun YOU , Kyung-Hoon KIM
发明人： Dong-Won PARK , Jae Sung BAE , Bonghyun YOU , Kyung-Hoon KIM
IPC分类号： G09G3/20 , G09G3/30 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G2310/0297 , G09G2320/0247 , G09G2330/021
摘要： A display apparatus includes a first pixel, a second pixel, a first selector, and a second selector. The first pixel includes first sub-pixels connected to a first gate line and respectively connected to corresponding data lines included in a first data line group and the second pixel includes second sub-pixels connected to a second gate line adjacent to the first gate line and respectively connected to corresponding data lines, one of which is included in a second data line group different from the first data line group. The first selector applies first data signals to one of odd-numbered data lines, and the second selector applies second data signals having a different polarity from the second data signals to one of even-numbered data lines.
摘要翻译：显示装置包括第一像素，第二像素，第一选择器和第二选择器。第一像素包括连接到第一栅极线并分别连接到包括在第一数据线组中的对应数据线的第一子像素，并且第二像素包括连接到与第一栅极线相邻的第二栅极线的第二子像素，以及分别连接到相应的数据线，其中一条数据线被包括在与第一数据线组不同的第二数据线组中。第一选择器将第一数据信号应用于奇数数据线之一，并且第二选择器将具有与第二数据信号不同的极性的第二数据信号应用于偶数数据线中的一个。

2. 发明申请

US20110187427A1 LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：延迟控制电路和包括其的半导体存储器件
公开(公告)号：US20110187427A1
公开(公告)日：2011-08-04
申请号：US12751671
申请日：2010-03-31
申请人： Kyung-Hoon KIM , Kyung-Whan Kim
发明人： Kyung-Hoon KIM , Kyung-Whan Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/06
摘要： A latency control circuit includes a delay unit configured to delay an input signal for a delay corresponding to a phase difference between an external clock and an internal clock and generate a delayed input signal, a delay information generation unit configured to generate a delay information based on a latency information and a delay amount of the input signal caused by a chip including the latency control circuit, a shift unit configured to shift the delayed input signal for a time period corresponding to the delay information in synchronism with the internal clock and an asynchronous control unit configured to selectively control the shift unit to output the delayed input signal without performing a shift operation.
摘要翻译：延迟控制电路包括：延迟单元，被配置为延迟与外部时钟和内部时钟之间的相位差对应的延迟的输入信号，并生成延迟的输入信号;延迟信息生成单元，被配置为基于延迟信息和由包括等待时间控制电路的芯片引起的输入信号的延迟量;移位单元，被配置为与延迟信号相对应的延迟输入信号与内部时钟同步地移位;异步控制单元，被配置为选择性地控制所述移位单元以输出所述延迟的输入信号，而不执行移位操作。

3. 发明申请

US20090045857A1 DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：延迟锁定环路
公开(公告)号：US20090045857A1
公开(公告)日：2009-02-19
申请号：US12255056
申请日：2008-10-21
申请人： Kyung-Hoon KIM
发明人： Kyung-Hoon KIM
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805 , H03L7/087
摘要： A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.
摘要翻译：延迟锁定环通过使用具有比DLL输出时钟更高级的相位的输出时钟来增加延迟锁定环的操作余量。时钟延迟补偿块接收外部时钟信号从而产生第一多时钟和第二多时钟。相位控制块将第一多时钟与第二多个时钟进行比较，以产生控制移位操作的相位控制信号。多相延迟控制块基于相位控制信号执行移位操作，以控制时钟延迟补偿块。

4. 发明申请

US20110204943A1 DELAY CELL AND PHASE LOCKED LOOP USING THE SAME 有权
标题翻译：延迟细胞和相位锁定环使用它
公开(公告)号：US20110204943A1
公开(公告)日：2011-08-25
申请号：US13102938
申请日：2011-05-06
申请人： Taek-Sang SONG , Kyung-Hoon KIM , Dae-Han KWON
发明人： Taek-Sang SONG , Kyung-Hoon KIM , Dae-Han KWON
IPC分类号： H03L7/08
CPC分类号： H03L7/0995 , H03K3/0322 , H03K5/133 , H03K2005/00208 , H03K2005/00234 , H03L2207/06
摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.
摘要翻译：通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

5. 发明申请

US20090273381A1 DELAYED LOCKED LOOP CIRCUIT 失效
标题翻译：延迟锁定环路
公开(公告)号：US20090273381A1
公开(公告)日：2009-11-05
申请号：US12164199
申请日：2008-06-30
申请人： Kyung-Hoon KIM , Bo-Kyeom Kim , Taek-Sang Song
发明人： Kyung-Hoon KIM , Bo-Kyeom Kim , Taek-Sang Song
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/087 , H03L7/091 , H03L7/093
摘要： A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device.
摘要翻译：用于补偿存储器件的相位偏移的延迟锁定环路包括：第一延迟锁定单元，被配置为将存储器件的外部时钟延迟第一延迟量以输出第一内部时钟;第二锁定单元，被配置为将外部时钟延迟第二延迟量以输出第二内部时钟，第二延迟量大于第一延迟量，以及选择单元，被配置为选择第一内部时钟和第二内部时钟之一作为存储器件的内部时钟。

6. 发明申请

US20120218831A1 INTEGRATED CIRCUIT FOR STORING INFORMATION 有权
标题翻译：集成电路存储信息
公开(公告)号：US20120218831A1
公开(公告)日：2012-08-30
申请号：US13331921
申请日：2011-12-20
申请人： Kyung-Hoon KIM
发明人： Kyung-Hoon KIM
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/22 , G11C5/147 , G11C7/062 , G11C7/067 , G11C7/106 , G11C7/1072 , G11C11/4091 , G11C16/0466 , G11C16/26
摘要： An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the control signal in a programming operation mode and an information detection unit configured to detect programming information in response to an output voltage of the variable resistance unit in a normal operation mode.
摘要翻译：集成电路包括：可变电阻单元，包括至少一个晶体管，其接收控制信号并响应于编程操作模式中的控制信号改变通过晶体管的电阻;以及信息检测单元，其被配置为响应于控制信号检测编程信息可变电阻单元的输出电压处于正常操作模式。

7. 发明申请

US20110238500A1 SYSTEM AND METHOD FOR EXPOSING ADVERTISEMENT BASED ON KEYWORD IN REAL TIME 审中-公开
标题翻译：基于关键字实时曝光广告的系统和方法
公开(公告)号：US20110238500A1
公开(公告)日：2011-09-29
申请号：US13074372
申请日：2011-03-29
申请人： Kyung-Hoon KIM
发明人： Kyung-Hoon KIM
IPC分类号： G06Q30/00
CPC分类号： G06Q30/0251 , G06Q30/02 , G06Q30/0256
摘要： Provided are a system and a method for exposing an advertisement based on a keyword in real time. The system may include an inventory determining unit to determine an inventory for each target keyword using a search log based on a keyword of a user, and an advertisement registering unit to register an advertisement into an inventory corresponding to a target keyword selected by an advertiser. The system may expose an advertisement while precisely reflecting a subject of interest of the user, thereby improving an advertising effect.
摘要翻译：提供了一种用于基于关键字实时曝光广告的系统和方法。系统可以包括库存确定单元，用于使用基于用户的关键字的搜索日志来确定每个目标关键字的库存;以及广告登记单元，用于将广告注册到与由广告商选择的目标关键字相对应的库存中。系统可以在精确地反映用户感兴趣的对象的同时曝光广告，从而改善广告效果。

8. 发明申请

US20090245325A1 SEMICONDUCTOR MEMORY DEVICE WITH TEMPERATURE SENSING DEVICE AND OPERATION THEREOF 有权
标题翻译：具有温度感测装置的半导体存储器件及其操作
公开(公告)号：US20090245325A1
公开(公告)日：2009-10-01
申请号：US12463838
申请日：2009-05-11
申请人： Kyung-Hoon KIM , Patrick B. Moran
发明人： Kyung-Hoon KIM , Patrick B. Moran
IPC分类号： G01K1/00
CPC分类号： G01K13/00 , G11C5/143 , G11C7/04 , G11C7/1051 , G11C7/106 , G11C7/20 , G11C11/406 , G11C11/40626 , G11C2029/5002 , G11C2211/4061
摘要： A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage unit stores output signals of the temperature sensing unit and outputs temperature values. The initializing unit initializes the storage unit after a predetermined time from an activation of the driving signal. A driving method includes driving the thermosensor in response to the driving signal, requesting a re-driving after a predetermined time from the activation of the driving signal, and re-driving the thermosensor in response to the driving signal input again.
摘要翻译：半导体存储器件包括感测器件的当前温度并确认温度值是否有效的热敏传感器。热敏传感器包括温度检测单元，存储单元和初始化单元。温度感测单元响应于驱动信号感测温度。存储单元存储温度感测单元的输出信号并输出温度值。初始化单元在从驱动信号的激活开始的预定时间之后初始化存储单元。驱动方法包括响应于驱动信号驱动热敏传感器，在从驱动信号的激活开始的预定时间之后请求重新驱动，并且响应于再次输入驱动信号重新驱动热敏传感器。

9. 发明申请

US20080180127A1 On-chip self test circuit and self test method for signal distortion 有权
公开(公告)号：US20080180127A1
公开(公告)日：2008-07-31
申请号：US12076890
申请日：2008-03-25
申请人： Kyung-Hoon KIM
发明人： Kyung-Hoon KIM
IPC分类号： G01R31/02
CPC分类号： G01R31/31708 , G01R31/3187 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12015 , G11C29/40 , G11C29/50 , G11C29/50012
摘要： There is provided an on-chip test circuit that is capable of measuring validity of an output signal within a chip without any external measuring device. The on-chip self test circuit implemented on the same chip as a test semiconductor device includes: a test load block for receiving a test target signal; and a self test block for receiving a test target signal passing through the test load block and a test target signal inputted to an output driver together, and determining whether a change of the test target signal is within an allowable range. Accordingly, the validity of the signal outputted from the device can be measured without any expensive external measuring device. Also, when the test must be done before the packaging stage, the test can be simply performed, thereby reducing the test cost greatly.

10. 发明申请

US20120014198A1 SEMICONDUCTOR MEMORY DEVICE WITH TEMPERATURE SENSING DEVICE CAPABLE OF MINIMIZING POWER CONSUMPTION IN REFRESH 有权
标题翻译：具有温度传感装置的半导体存储器件，能够最小化刷新功耗
公开(公告)号：US20120014198A1
公开(公告)日：2012-01-19
申请号：US13240136
申请日：2011-09-22
申请人： Kyung-Hoon KIM , Patrick B. Moran
发明人： Kyung-Hoon KIM , Patrick B. Moran
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C11/406 , G11C11/40626 , G11C2029/5002 , G11C2211/4067
摘要： A semiconductor memory device capable of measuring a temperature without the influence of noise includes a temperature sensing device for sensing a current temperature in response to a control signal, wherein the semiconductor memory device enters a power save mode for a predetermined time starting from an activation of the control signal and wherein the power save mode has substantially no power consumption. A method for driving a semiconductor memory device in accordance with the present invention includes sensing a current temperature in response to a control signal and entering a power save mode for a predetermined time starting from an activation of the control signal, wherein the power save mode has substantially no power consumption.
摘要翻译：能够在不受噪声影响的情况下测量温度的半导体存储器件包括用于响应于控制信号感测当前温度的温度感测装置，其中半导体存储器件从激活时开始预定的时间进入省电模式所述控制信号并且其中所述省电模式基本上没有功率消耗。根据本发明的用于驱动半导体存储器件的方法包括响应于控制信号感测当前温度并且从控制信号的激活开始预定时间进入省电模式，其中省电模式具有基本上没有功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式