专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09425198B2 Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same 有权
标题翻译：具有应变松弛缓冲层的半导体器件及其制造方法
公开(公告)号：US09425198B2
公开(公告)日：2016-08-23
申请号：US14289672
申请日：2014-05-29
申请人： Dong-Kyu Lee , Jae-Hwan Lee , Tae-Yong Kwon , Sang-Su Kim , Jung-Dal Choi
发明人： Dong-Kyu Lee , Jae-Hwan Lee , Tae-Yong Kwon , Sang-Su Kim , Jung-Dal Choi
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/8252 , H01L21/8258 , H01L27/06
CPC分类号： H01L27/0928 , H01L21/823807 , H01L21/823892 , H01L21/8252 , H01L21/8258 , H01L27/0605 , H01L29/1054 , H01L29/161 , H01L29/20
摘要： A semiconductor device includes a substrate, a strain-relaxed buffer layer on the substrate, at least one well in the strain-relaxed buffer layer, a first channel layer on the strain-relaxed buffer layer, and a second channel layer on the well. A lattice constant of material constituting the first well is less than a lattice constant of the material constituting the strain-relaxed buffer layer, but a lattice constant of material constituting the second well is greater than the lattice constant of the material constituting the strain-relaxed buffer layer.
摘要翻译：半导体器件包括衬底，衬底上的应变松弛缓冲层，应变松弛缓冲层中的至少一个阱，应变松弛缓冲层上的第一沟道层和阱上的第二沟道层。构成第一阱的材料的晶格常数小于构成应变弛缓缓冲层的材料的晶格常数，但构成第二阱的材料的晶格常数大于构成应变弛豫缓冲层的材料的晶格常数缓冲层。

2. 发明授权

US09450049B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09450049B2
公开(公告)日：2016-09-20
申请号：US14276421
申请日：2014-05-13
申请人： Tae-Yong Kwon , Sang-Su Kim , Jung-Gil Yang , Jung-Dal Choi
发明人： Tae-Yong Kwon , Sang-Su Kim , Jung-Gil Yang , Jung-Dal Choi
IPC分类号： H01L27/00 , H01L29/10 , H01L29/205 , H01L29/78 , H01L29/165 , H01L27/088 , H01L21/8238 , H01L21/84 , H01L29/66 , H01L27/092 , H01L27/12
CPC分类号： H01L29/1054 , H01L21/823821 , H01L21/845 , H01L27/088 , H01L27/0924 , H01L27/1211 , H01L29/165 , H01L29/20 , H01L29/205 , H01L29/66522 , H01L29/6681 , H01L29/78 , H01L29/7842 , H01L29/785
摘要： A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material.
摘要翻译：半导体器件包括衬底，化合物半导体层以及第一和第二半导体图案。衬底包括第一和第二区域。第一半导体图案在第一区域的化合物半导体层上，并且包括元件半导体。第二半导体图案在第二区域的化合物半导体层上，并且包括III-V族半导体材料。

3. 发明申请

US20150279995A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150279995A1
公开(公告)日：2015-10-01
申请号：US14669082
申请日：2015-03-26
申请人： Shigenobu Maeda , Tae-Yong Kwon , Sang-Su Kim , Jae-Hoo Park
发明人： Shigenobu Maeda , Tae-Yong Kwon , Sang-Su Kim , Jae-Hoo Park
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/823431 , H01L21/823437 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
摘要翻译：形成半导体器件的方法可以包括形成在衬底上沿第一方向延伸的鳍式有源图案，鳍型有源图案包括在衬底上的下图案和下图案上的上图案。场绝缘层形成在衬底上，翅片型有源图案的侧壁和远离衬底的部分上部图案远离场绝缘层的顶表面。形成与翅片型有源图案相交并且沿与第一方向不同的第二方向延伸的伪栅极图案。所述方法包括在伪栅极图案的侧壁上形成虚拟栅极间隔物，在虚拟栅极图案的两侧上形成鳍状有源图案中的凹槽，并在虚拟栅极图案的两侧形成源区和漏极区。

4. 发明授权

US09431537B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09431537B2
公开(公告)日：2016-08-30
申请号：US14669082
申请日：2015-03-26
申请人： Shigenobu Maeda , Tae-Yong Kwon , Sang-Su Kim , Jae-Hoo Park
发明人： Shigenobu Maeda , Tae-Yong Kwon , Sang-Su Kim , Jae-Hoo Park
IPC分类号： H01L31/072 , H01L31/109 , H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L27/092 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/823431 , H01L21/823437 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
摘要翻译：形成半导体器件的方法可以包括形成在衬底上沿第一方向延伸的鳍式有源图案，鳍型有源图案包括在衬底上的下图案和下图案上的上图案。场绝缘层形成在衬底上，翅片型有源图案的侧壁和远离衬底的部分上部图案远离场绝缘层的顶表面。形成与翅片型有源图案相交并且沿与第一方向不同的第二方向延伸的伪栅极图案。所述方法包括在伪栅极图案的侧壁上形成虚拟栅极间隔物，在虚拟栅极图案的两侧上形成鳍状有源图案中的凹槽，并在虚拟栅极图案的两侧形成源区和漏极区。

5. 发明申请

US20160307927A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160307927A1
公开(公告)日：2016-10-20
申请号：US14993212
申请日：2016-01-12
申请人： Jung-Han Lee , Jae-Hwan Lee , Sang-Su Kim , Hwan-Wook Choi , Tae-Jong Lee , Seung-Mo Ha
发明人： Jung-Han Lee , Jae-Hwan Lee , Sang-Su Kim , Hwan-Wook Choi , Tae-Jong Lee , Seung-Mo Ha
IPC分类号： H01L27/12 , H01L29/06 , H01L27/088
CPC分类号： H01L29/0657 , H01L21/823431 , H01L21/823468 , H01L27/0886
摘要： A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
摘要翻译：半导体器件包括由衬底上的隔离层限定的多个有源散热片，活性散热片上的栅极结构和隔离层，以及覆盖栅极结构的侧壁的栅极间隔结构。栅极结构的侧壁分别包括具有第一，第二和第三斜率的第一，第二和第三区域。第二斜坡从底部向第二区域的顶部增加。第二斜坡在第二区域的底部具有小于第一斜坡的值。第三斜率大于第二斜率。

6. 发明授权

US07170794B2 Programming method of a non-volatile memory device having a charge storage layer between a gate electrode and a semiconductor substrate 失效
标题翻译：在栅电极和半导体衬底之间具有电荷存储层的非易失性存储器件的编程方法
公开(公告)号：US07170794B2
公开(公告)日：2007-01-30
申请号：US10971201
申请日：2004-10-21
申请人： Ki-Chul Kim , Byou-Ree Lim , Sang-Su Kim , Geum-Jong Bae , Kwang-Wook Koh
发明人： Ki-Chul Kim , Byou-Ree Lim , Sang-Su Kim , Geum-Jong Bae , Kwang-Wook Koh
IPC分类号： G11C11/34
CPC分类号： G11C16/0425
摘要： A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.
摘要翻译：非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。

7. 发明授权

US07045850B2 Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same 有权
标题翻译：具有浮动阱式非易失性存储单元的半导体器件及其制造方法
公开(公告)号：US07045850B2
公开(公告)日：2006-05-16
申请号：US10844783
申请日：2004-05-13
申请人： Sang-Su Kim , Kwang-Wook Koh , Geum-Jong Bae , Ki-Chul Kim , Sung-Ho Kim , Jin-Hee Kim , In-Wook Cho
发明人： Sang-Su Kim , Kwang-Wook Koh , Geum-Jong Bae , Ki-Chul Kim , Sung-Ho Kim , Jin-Hee Kim , In-Wook Cho
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L21/823462 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.
摘要翻译：本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。依次形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层构成的三层，然后除去非易失性存储区域之外的半导体衬底上的三层。第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

8. 发明申请

US20050186734A1 Method of manufacturing a non-volatile semiconductor memory device 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US20050186734A1
公开(公告)日：2005-08-25
申请号：US10786239
申请日：2004-02-24
申请人： In-Wook Cho , Nae-In Lee , Kwang-Wook Koh , Geun-Jong Bae , Sang-Su Kim , Jin-Hee Kim , Sung-Ho Kim , Ki-Chul Kim
发明人： In-Wook Cho , Nae-In Lee , Kwang-Wook Koh , Geun-Jong Bae , Sang-Su Kim , Jin-Hee Kim , Sung-Ho Kim , Ki-Chul Kim
IPC分类号： H01L27/10 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11568 , Y10S438/954
摘要： A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.
摘要翻译：制造非易失性半导体存储器件的方法是通过在衬底上形成具有ONO组成的电介质层图案而开始的。在包括在电介质层图案上的衬底上形成多晶硅层。图案化多晶硅层以形成暴露部分介电层图案的分裂多晶硅层图案。暴露的电介质层被蚀刻，然后使用分离多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源区。

9. 发明申请

US20050184334A1 Non-volatile memory device having a charge storage oxide layer and operation thereof 失效
标题翻译：具有电荷存储氧化物层的非易失性存储器件及其操作
公开(公告)号：US20050184334A1
公开(公告)日：2005-08-25
申请号：US11047764
申请日：2005-02-02
申请人： Ki-Chul Kim , Geum-Jong Bae , Byoung-jin Lee , Sang-Su Kim
发明人： Ki-Chul Kim , Geum-Jong Bae , Byoung-jin Lee , Sang-Su Kim
IPC分类号： H01L27/115 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/792
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain regions. A gate electrode is disposed on the charge storage oxide layer. At least one halo implantation region is formed in the semiconductor substrate adjacent to one of the pair of source/drain regions, and overlapping the charge storage oxide layer. A program operation is performed by trapping electrons in the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed, and an erase operation is performed by injecting holes into the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed.
摘要翻译：非易失性存储器件包括设置在半导体衬底中的一对源极/漏极区域，它们之间具有沟道区域。电荷存储氧化物层设置在沟道区上，并且与一对源极/漏极区的每一个的一部分重叠。栅电极设置在电荷存储氧化物层上。至少一个卤素注入区域形成在与一对源极/漏极区域中的一个相邻的半导体衬底中，并与电荷存储氧化物层重叠。通过在位于形成有卤素离子注入区域的源极/漏极区附近的电荷存储氧化物层中俘获电子来执行编程操作，并且通过将空穴注入位于源/漏区附近的电荷存储氧化物层中来执行擦除操作，漏区，其中形成有卤素离子注入区。

10. 发明申请

US20050088879A1 Programming method of a non-volatile memory device having a charge storage layer between a gate electrode and a semiconductor substrate 失效
标题翻译：在栅电极和半导体衬底之间具有电荷存储层的非易失性存储器件的编程方法
公开(公告)号：US20050088879A1
公开(公告)日：2005-04-28
申请号：US10971201
申请日：2004-10-21
申请人： Ki-Chul Kim , Byou-Ree Lim , Sang-Su Kim , Geum-Jong Bae , Kwang-Wook Koh
发明人： Ki-Chul Kim , Byou-Ree Lim , Sang-Su Kim , Geum-Jong Bae , Kwang-Wook Koh
IPC分类号： H01L27/115 , G11C16/04 , G11C11/34
CPC分类号： G11C16/0425
摘要： A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.
摘要翻译：非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式