专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08074352B2 Method of manufacturing printed circuit board 失效
标题翻译：制造印刷电路板的方法
公开(公告)号：US08074352B2
公开(公告)日：2011-12-13
申请号：US12213365
申请日：2008-06-18
申请人： Dong-Jin Park , Seung-Hyun Jung , Seung-Chul Kim , Soon-Jin Cho
发明人： Dong-Jin Park , Seung-Hyun Jung , Seung-Chul Kim , Soon-Jin Cho
IPC分类号： H05K3/04 , H05K3/06 , H05K3/42
CPC分类号： H05K3/107 , H05K3/0035 , H05K3/0038 , H05K3/045 , H05K3/421 , H05K3/427 , H05K2201/0394 , H05K2201/09563 , H05K2203/0577 , H05K2203/0723 , H05K2203/1152 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of manufacturing a printed circuit board is disclosed. The method may include: sequentially stacking an acid-resistant first cover layer and an alkali-resistant second cover layer over a copper foil, for a copper clad laminate that includes the copper foil stacked over one side of an insulation layer; forming an intaglio groove by removing portions of the second cover layer, the first cover layer, and the copper clad laminate; stacking a seed layer over the intaglio groove and the second cover layer; removing a portion of the seed layer stacked over the second cover layer, by stripping the second cover layer; forming a plating layer, by plating an inside of the intaglio groove; stripping the first cover layer; and removing the copper foil exposed by the stripping of the first cover layer.
摘要翻译：公开了一种制造印刷电路板的方法。该方法可以包括：在铜箔上顺序层叠耐酸性第一覆盖层和耐碱性第二覆盖层，对于包含层叠在绝缘层一侧的铜箔的覆铜层压板，通过去除第二覆盖层，第一覆盖层和覆铜层压板的部分来形成凹版凹槽; 将种子层堆叠在凹版凹槽和第二覆盖层上; 通过剥离所述第二覆盖层去除层叠在所述第二覆盖层上的所述种子层的一部分; 通过电镀凹版凹槽的内部形成镀层; 剥离第一覆盖层; 以及去除通过剥离第一覆盖层而暴露的铜箔。

2. 发明申请

US20090133253A1 Method of manufacturing printed circuit board 失效
标题翻译：制造印刷电路板的方法
公开(公告)号：US20090133253A1
公开(公告)日：2009-05-28
申请号：US12213365
申请日：2008-06-18
申请人： Dong-Jin Park , Seung-Hyun Jung , Seung-Chul Kim , Soon-Jin Cho
发明人： Dong-Jin Park , Seung-Hyun Jung , Seung-Chul Kim , Soon-Jin Cho
IPC分类号： H05K3/12 , H01B13/00
CPC分类号： H05K3/107 , H05K3/0035 , H05K3/0038 , H05K3/045 , H05K3/421 , H05K3/427 , H05K2201/0394 , H05K2201/09563 , H05K2203/0577 , H05K2203/0723 , H05K2203/1152 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A method of manufacturing a printed circuit board is disclosed. The method may include: sequentially stacking an acid-resistant first cover layer and an alkali-resistant second cover layer over a copper foil, for a copper clad laminate that includes the copper foil stacked over one side of an insulation layer; forming an intaglio groove by removing portions of the second cover layer, the first cover layer, and the copper clad laminate; stacking a seed layer over the intaglio groove and the second cover layer; removing a portion of the seed layer stacked over the second cover layer, by stripping the second cover layer; forming a plating layer, by plating an inside of the intaglio groove; stripping the first cover layer; and removing the copper foil exposed by the stripping of the first cover layer.
摘要翻译：公开了一种制造印刷电路板的方法。该方法可以包括：在铜箔上顺序层叠耐酸性第一覆盖层和耐碱性第二覆盖层，对于包含层叠在绝缘层一侧的铜箔的覆铜层压板，通过去除第二覆盖层，第一覆盖层和覆铜层压板的部分来形成凹版凹槽; 将种子层堆叠在凹版凹槽和第二覆盖层上; 通过剥离所述第二覆盖层去除层叠在所述第二覆盖层上的所述种子层的一部分; 通过电镀凹版凹槽的内部形成镀层; 剥离第一覆盖层; 以及去除通过剥离第一覆盖层而暴露的铜箔。

3. 发明申请

US20090136656A1 Method of manufacturing printed circuit board 审中-公开
标题翻译：制造印刷电路板的方法
公开(公告)号：US20090136656A1
公开(公告)日：2009-05-28
申请号：US12213700
申请日：2008-06-23
申请人： Dong-Jin Park , Seung-Hyun Jung , Seung-Chul Kim , Soon-Jin Cho
发明人： Dong-Jin Park , Seung-Hyun Jung , Seung-Chul Kim , Soon-Jin Cho
IPC分类号： H05K3/02
CPC分类号： H05K3/427 , H05K3/0035 , H05K3/0038 , H05K3/421 , H05K2201/0175 , H05K2201/0394 , H05K2201/09563 , H05K2203/1152
摘要： A method of manufacturing a printed circuit board is disclosed. The method may include: stacking an anti-plating layer over a copper foil, for a copper clad laminate that includes the copper foil stacked over one side of an insulation layer; forming an intaglio groove, by removing a portion of the anti-plating layer and a portion of the copper clad laminate; stacking a seed layer over a surface of the intaglio groove; forming a plating layer, by plating an inside of the intaglio groove; and removing the anti-plating layer and the copper foil.
摘要翻译：公开了一种制造印刷电路板的方法。该方法可以包括：在铜箔上堆叠防镀层，对于包括层叠在绝缘层的一侧上的铜箔的覆铜层压板; 通过去除所述防镀层的一部分和所述覆铜层压板的一部分来形成凹版凹槽; 将种子层堆叠在凹版凹槽的表面上; 通过电镀凹版凹槽的内部形成镀层; 并且去除防镀层和铜箔。

4. 发明申请

US20090134118A1 Method of manufacturing printed circuit board 审中-公开
标题翻译：制造印刷电路板的方法
公开(公告)号：US20090134118A1
公开(公告)日：2009-05-28
申请号：US12213699
申请日：2008-06-23
申请人： Dong-Jin Park , Seung-Hyun Jung , Seung-Chul Kim , Sooh-Jin Cho
发明人： Dong-Jin Park , Seung-Hyun Jung , Seung-Chul Kim , Sooh-Jin Cho
IPC分类号： H01B13/00
CPC分类号： H05K3/107 , H05K3/0035 , H05K3/0038 , H05K3/045 , H05K3/421 , H05K3/427 , H05K2201/0394 , H05K2201/09563 , H05K2203/025 , H05K2203/0723 , H05K2203/1152
摘要： A method of manufacturing a printed circuit board is disclosed. The method may include: stacking a cover layer over a copper foil, for a copper clad laminate that includes the copper foil stacked over one side of an insulation layer; forming an intaglio groove by removing portions of the cover layer and the copper clad laminate; stacking a seed layer over a surface of the intaglio groove and the cover layer; removing a portion of the seed layer stacked over the cover layer, by removing a portion of the cover layer; forming a plating layer, by plating an inside of the intaglio groove; and removing the remaining cover layer and the copper foil.
摘要翻译：公开了一种制造印刷电路板的方法。该方法可以包括：在铜箔上堆叠覆盖层，用于包括在绝缘层的一侧上堆叠的铜箔的覆铜层压板; 通过去除覆盖层和覆铜层压板的部分形成凹版凹槽; 将种子层堆叠在凹版凹槽和覆盖层的表面上; 通过去除覆盖层的一部分来去除层叠在覆盖层上的种子层的一部分; 通过电镀凹版凹槽的内部形成镀层; 并除去剩余的覆盖层和铜箔。

5. 发明申请

US20090120660A1 Electrical member and method of manufacturing a printed circuit board using the same 审中-公开
标题翻译：电气部件及使用其的印刷电路板的制造方法
公开(公告)号：US20090120660A1
公开(公告)日：2009-05-14
申请号：US12081864
申请日：2008-04-22
申请人： Dong-Jin Park , Chung-Woo Cho , Seung-Chul Kim , Chang-Sup Ryu
发明人： Dong-Jin Park , Chung-Woo Cho , Seung-Chul Kim , Chang-Sup Ryu
IPC分类号： H01B3/30 , H05K3/10
CPC分类号： H05K3/045 , H05K3/0032 , H05K3/107 , H05K2201/0376 , H05K2201/09036 , H05K2201/09045 , H05K2203/0723 , Y10T29/49155
摘要： An electrical member and a method of manufacturing a printed circuit board using the electrical member are disclosed. The method includes: forming an intaglio groove in an insulation layer, where the intaglio groove has at least one protrusion formed within; stacking a seed layer over the intaglio groove; forming a plating layer by performing electroplating over the seed layer; and forming a circuit pattern, which includes the plating layer filled in the intaglio groove, by removing a portion of the plating layer such that the insulation layer is exposed.
摘要翻译：公开了一种使用电气部件的电气部件和制造印刷电路板的方法。该方法包括：在绝缘层中形成凹版凹槽，凹版凹槽中形成有至少一个凸起; 将种子层堆叠在凹版凹槽上; 通过在种子层上进行电镀来形成镀层; 以及通过去除所述镀层的一部分使得所述绝缘层暴露的方式形成包括填充在所述凹版凹槽中的镀层的电路图案。

6. 发明授权

US08808958B2 Process for preparing polymerized toner 有权
标题翻译：制备聚合调色剂的方法
公开(公告)号：US08808958B2
公开(公告)日：2014-08-19
申请号：US13243981
申请日：2011-09-23
申请人： Wook Jang , Chang-Soon Lee , Dong-Jin Park , Jung-Woo Kim
发明人： Wook Jang , Chang-Soon Lee , Dong-Jin Park , Jung-Woo Kim
IPC分类号： G03G9/08
CPC分类号： G03G9/0806 , G03G9/08708 , G03G9/08711 , G03G9/08782 , G03G9/08788 , G03G9/08795 , G03G9/08797 , G03G9/0904 , G03G9/0918
摘要： The present invention relates to a process for preparing a polymerized toner, and in particular to a process for preparing a polymerized toner and a polymerized toner prepared therefrom, wherein a certain block copolymer and copper phthalocyanine are used within a predetermined range of the amounts for a carbon black dispersant during a suspension polymerization, thereby making it possible to realize a narrow particle sizes distribution, high transcription efficiency, and an enhanced image concentration.
摘要翻译：本发明涉及一种制备聚合调色剂的方法，特别涉及一种制备聚合调色剂和由其制备的聚合调色剂的方法，其中在预定范围内使用某种嵌段共聚物和铜酞菁，其量为炭黑分散剂，从而可以实现窄的粒度分布，高的转录效率和增强的图像浓度。

7. 发明授权

US08549744B2 Printed circuit board using bump and method for manufacturing thereof 失效
标题翻译：使用凸块的印刷电路板及其制造方法
公开(公告)号：US08549744B2
公开(公告)日：2013-10-08
申请号：US11727838
申请日：2007-03-28
申请人： Hee-Bum Shin , Dong-Jin Park , Jee-Soo Mok , Jong-Suk Bae , Ki-Hwan Kim
发明人： Hee-Bum Shin , Dong-Jin Park , Jee-Soo Mok , Jong-Suk Bae , Ki-Hwan Kim
IPC分类号： H01K3/10
CPC分类号： H05K3/462 , H05K3/4069 , H05K3/423 , H05K3/4623 , H05K3/4647 , H05K3/4652 , H05K2201/09563 , H05K2203/0733 , H05K2203/1492 , Y10T29/49165
摘要： The present invention provides a method for manufacturing a printed circuit board and a print circuit board manufactured thereby, in which through holes of a core board are filled by reverse pulse plating so that it allows to manufacture a core board having greater than 100 μm of a thickness which has been a processing limitation with conventional technologies and form bumps on a thick insulation layer, which has been difficult till now, and thus providing resistance against pressure of paste bumps produced during stacking due to the increased strength of a core board, convenience to join between layers, excellent heat-releasing effect, and collectively stacking of core boards, which was not possible with conventional methods.
摘要翻译：本发明提供一种制造印刷电路板的方法和由此制造的印刷电路板，其中通过反向脉冲电镀填充芯板的通孔，从而允许制造具有大于100μm的在现有技术难以达到现有技术的加工限制以及在厚绝缘层上形成凸块的厚度，由于芯板的强度提高，堆叠时产生的焊膏凸起的压力抵抗力提高，层之间的连接，散热效果优异，并且集体堆叠芯板，这对于常规方法是不可能的。

8. 发明授权

US08443203B2 Secure boot method and semiconductor memory system using the method 有权
标题翻译：使用该方法的安全引导方法和半导体存储器系统
公开(公告)号：US08443203B2
公开(公告)日：2013-05-14
申请号：US12145102
申请日：2008-06-24
申请人： Dong-Jin Park , Hyo-Sun Hwang , Myung-Hee Kang , Won-Il Lee
发明人： Dong-Jin Park , Hyo-Sun Hwang , Myung-Hee Kang , Won-Il Lee
IPC分类号： G06F21/00
CPC分类号： G06F21/575
摘要： A semiconductor memory system includes an external memory, an internal memory, and a one-time programmable (OTP) memory. The external memory includes a kernel, a public key, first boot information used to authenticate the public key and generate a test secret key, and a second boot loader verifying integrity of the kernel. The internal memory includes a first boot loader that verifies integrity of the second boot loader and generates the test secret key. The OTP memory includes second boot information generated using the public key and a secret key. Since the secure boot method and the semiconductor memory system using the method do not need an additional OTP memory to store a secret key unlike conventional technology, the capacity and recording time of the OTP memory can be reduced to about half compared to the conventional technology.
摘要翻译：半导体存储器系统包括外部存储器，内部存储器和一次性可编程（OTP）存储器。外部存储器包括内核，公共密钥，用于认证公钥并生成测试密钥的第一引导信息，以及验证内核完整性的第二引导加载程序。内部存储器包括第一引导加载程序，其验证第二引导加载程序的完整性并生成测试密钥。 OTP存储器包括使用公钥和秘密密钥生成的第二引导信息。由于与常规技术不同，使用该方法的安全引导方法和半导体存储器系统不需要额外的OTP存储器来存储秘密密钥，所以与常规技术相比，OTP存储器的容量和记录时间可以减少到大约一半。

9. 发明授权

US08200293B2 Mobile phone cradle and vehicle including the same 有权
标题翻译：手机摇篮和车载包括相同
公开(公告)号：US08200293B2
公开(公告)日：2012-06-12
申请号：US12622960
申请日：2009-11-20
申请人： Dong-Jin Park , Byung Kyu Yoon , Hong Sik Chang , Hun Soo Kim , Hae Ryong Kim , Hee Jun Jeong
发明人： Dong-Jin Park , Byung Kyu Yoon , Hong Sik Chang , Hun Soo Kim , Hae Ryong Kim , Hee Jun Jeong
IPC分类号： H04M1/00
CPC分类号： B60R11/0241 , B60R2011/0007 , B60R2011/0071 , B60R2011/0082 , B60R2011/0085 , H04M1/6075
摘要： A mobile phone cradle may include a housing, a lower body displaceably received in the housing, an upper body rotatably fixed to an upper portion of the lower body and displaceably received in the housing, wherein a mobile phone is held on the upper body, a first elastic member, wherein one end of the first elastic member is selectively wound around a roller rotatably mounted on the housing to move the lower body upwards and the other end of the elastic member is fixed to the lower body, a fixing member selectively fixing the lower body to the housing, and a moving unit guiding displacement of the lower body along the housing, wherein the upper body is rotated at a predetermined angle when taken out of the housing by the first elastic member.
摘要翻译：手机支架可以包括壳体，可移动地容纳在壳体中的下体，上体可旋转地固定到下体的上部并且可移动地容纳在壳体中，其中移动电话被保持在上身上，第一弹性构件，其中，第一弹性构件的一端被选择性地卷绕在可旋转地安装在壳体上的滚子周围，以使下体向上移动，弹性构件的另一端固定到下主体，固定构件选择性地固定以及移动单元引导下体沿着壳体的位移，其中当通过第一弹性构件从壳体中取出时，上身以预定的角度旋转。

10. 发明授权

US07973248B2 Printed circuit board using paste bump and manufacturing method thereof 有权
标题翻译：使用糊状凸块的印刷电路板及其制造方法
公开(公告)号：US07973248B2
公开(公告)日：2011-07-05
申请号：US12219381
申请日：2008-07-21
申请人： Jee-Soo Mok , Chang-Sup Ryu , Eung-Suek Lee , Youn-Soo Seo , Hee-Bum Shin , Yoong Oh , Byung-Bae Seo , Tae-Kyoung Kim , Dong-Jin Park
发明人： Jee-Soo Mok , Chang-Sup Ryu , Eung-Suek Lee , Youn-Soo Seo , Hee-Bum Shin , Yoong Oh , Byung-Bae Seo , Tae-Kyoung Kim , Dong-Jin Park
IPC分类号： H01R12/04 , H05K1/11
CPC分类号： H05K3/462 , H01R12/523 , H05K3/4069 , H05K3/4647 , H05K3/4652 , H05K2201/0355 , H05K2201/09509 , H05K2201/09536 , H05K2201/096 , H05K2203/0353 , Y10T29/49155
摘要： A printed circuit board using paste bumps and manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board using paste bumps, includes: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.
摘要翻译：公开了一种使用糊状凸块的印刷电路板及其制造方法。使用糊状凸块制造印刷电路板的方法包括：（a）穿孔芯板以形成至少一个通孔，（b）通过填充电镀填充至少一个通孔并在其上形成电路图案芯板的至少一个表面，（c）在芯板的至少一个表面上堆叠焊料凸块，以及（d）在焊料凸块的表面上形成外层电路，结构稳定的全层由于镀层芯板的BVH的强度增加，可以实现IVH结构，由于并行处理和集体堆叠，制造时间可以减少，由于粘贴凸块的铜箔堆叠而实现微电路变得容易在最外层，可以减少制造成本，因为可以省略某些电镀和钻孔工艺，在电路图案之间增加层间连接面积以提高连接可靠性，并且可以获得凹坑覆盖 d。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式