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1. 发明授权

US08396682B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08396682B2
公开(公告)日：2013-03-12
申请号：US12900547
申请日：2010-10-08
申请人： Chi-Sung Oh , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
发明人： Chi-Sung Oh , Dong-Hyuk Lee , Ho-Cheol Lee , Jang-Woo Ryu , Jung-Bae Lee
IPC分类号： G01R27/28 , G06F19/00
CPC分类号： G01R31/2884 , G01R31/31726
摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.
摘要翻译：提供半导体器件。半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

2. 发明授权

US08166238B2 Method, device, and system for preventing refresh starvation in shared memory bank 有权
标题翻译：用于防止共享存储器中刷新不足的方法，设备和系统
公开(公告)号：US08166238B2
公开(公告)日：2012-04-24
申请号：US11977047
申请日：2007-10-23
申请人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G11C7/1075 , G11C11/40603 , G11C11/40618
摘要： A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.
摘要翻译：多端口存储器件包括刷新寄存器和刷新控制器，用于防止存储器件的共享存储器单元中的刷新不足。存储装置还包括共享对共享存储器单元的访问的多个端口。刷新寄存器存储关于至少一个刷新命令的信息。刷新控制器根据存储在刷新寄存器中的信息来确定是否在端口权限转换时激活内部刷新操作。

3. 发明申请

US20120126840A1 Semiconductor Device with Cross-shaped Bumps and Test Pads Alignment 审中-公开
标题翻译：具有十字形碰撞的半导体器件和测试焊盘对准
公开(公告)号：US20120126840A1
公开(公告)日：2012-05-24
申请号：US13240738
申请日：2011-09-22
申请人： Dong-Hyuk Lee , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Chi-Sung Oh
IPC分类号： G01R31/3187
CPC分类号： G11C29/48 , G11C29/1201 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/50 , H01L2224/0346 , H01L2224/0362 , H01L2224/0401 , H01L2224/0557 , H01L2224/1146 , H01L2224/11622 , H01L2224/13005 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/14136 , H01L2224/16146 , H01L2224/16225 , H01L2224/81193 , H01L2224/81815 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01055 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/13099 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate; bumps disposed in a plurality of rows along a first axis direction of the semiconductor substrate; and test pads disposed in one or more columns along a second axis direction perpendicular to the first axis direction. The bumps and the test pads form a cross shape in the center portion of the semiconductor substrate. Disposing bumps in the central portion of the semiconductor substrate facilitates forming physical connections between stacked semiconductor devices of a semiconductor stack, regardless of the chip sizes.
摘要翻译：半导体器件包括半导体衬底; 沿着半导体衬底的第一轴线方向设置成多行的凸块; 以及沿着垂直于第一轴线方向的第二轴线方向设置在一个或多个列中的测试焊盘。凸块和测试焊盘在半导体衬底的中心部分形成十字形。在半导体衬底的中心部分设置凸起有助于在半导体堆叠的堆叠半导体器件之间形成物理连接，而与芯片尺寸无关。

4. 发明申请

US20100177576A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100177576A1
公开(公告)日：2010-07-15
申请号：US12686561
申请日：2010-01-13
申请人： Chi-Sung Oh , Jung-Bae Lee , Dong-Hyuk Lee
发明人： Chi-Sung Oh , Jung-Bae Lee , Dong-Hyuk Lee
IPC分类号： G11C7/08
CPC分类号： G11C7/065 , G11C5/025 , G11C7/08 , G11C11/4091
摘要： A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.
摘要翻译：半导体存储器件包括读出放大器，读出放大器驱动信号驱动器和控制器。读出放大器被配置为响应于读出放大器驱动信号来检测和放大位线的信号和互补位线的信号。读出放大器驱动信号驱动器包括：第一驱动信号驱动器，被配置为响应于第一读出放大器控制信号经由传输线驱动读出放大器驱动信号;以及第二驱动信号驱动器，被配置为通过传输线驱动读出放大器响应于第二读出放大器控制信号的驱动信号。控制器响应于有效命令激活第一读出放大器控制信号，并且在第一读出放大器控制信号被激活时切换第二读出放大器控制信号。

5. 发明授权

US07929369B2 Semiconductor memory device having refresh circuit and word line activating method therefor 失效
标题翻译：具有刷新电路和字线激活方法的半导体存储器件
公开(公告)号：US07929369B2
公开(公告)日：2011-04-19
申请号：US12453164
申请日：2009-04-30
申请人： Dong-Hyuk Lee , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Chi-Sung Oh
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/4085
摘要： A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block.
摘要翻译：半导体存储器件包括具有至少一个存储体的存储单元阵列。存储体被分成存储块，使得存储块具有块位置，该块位置包括在存储体的边缘处的至少一个边缘存储器块和至少一个非边缘存储器块。每个存储块包括多个存储单元。每个存储器单元与至少一个位线和至少一个字线相关联。所述半导体存储器件包括刷新执行电路，所述刷新执行电路被配置为在所述边缘存储器块中的存储器单元的刷新操作期间一次一个地激活小于或等于数量的字线，非边缘存储器块中的存储单元。

6. 发明申请

US20090296510A1 Semiconductor memory device having refresh circuit and word line activating method therefor 失效
标题翻译：具有刷新电路和字线激活方法的半导体存储器件
公开(公告)号：US20090296510A1
公开(公告)日：2009-12-03
申请号：US12453164
申请日：2009-04-30
申请人： Dong-Hyuk Lee , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Chi-Sung Oh
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/4085
摘要： A semiconductor memory device includes a memory cell array having at least one memory bank. The memory bank being divided into memory blocks such that the memory blocks have a block position including at least one edge memory block at an edge of the memory bank and at least one non-edge memory block. Each memory block includes a plurality of memory cells. Each memory cell associated with at least one bit line and at least one word line. The semiconductor memory device includes a refresh execution circuit configured to activate a less than or equal number of word lines one at a time during a refresh operation for the memory cells in the edge memory block as activated one at a time during a refresh operation for the memory cells in the non-edge memory block.
摘要翻译：半导体存储器件包括具有至少一个存储体的存储单元阵列。存储体被分成存储块，使得存储块具有块位置，该块位置包括在存储体的边缘处的至少一个边缘存储器块和至少一个非边缘存储器块。每个存储块包括多个存储单元。每个存储器单元与至少一个位线和至少一个字线相关联。所述半导体存储器件包括刷新执行电路，所述刷新执行电路被配置为在所述边缘存储器块中的存储器单元的刷新操作期间一次一个地激活小于或等于数量的字线，非边缘存储器块中的存储单元。

7. 发明申请

US20090106503A1 Method, device, and system for preventing refresh starvation in shared memory bank 有权
标题翻译：用于防止共享存储器中刷新不足的方法，设备和系统
公开(公告)号：US20090106503A1
公开(公告)日：2009-04-23
申请号：US11977047
申请日：2007-10-23
申请人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
发明人： Dong-Hyuk Lee , Kyung-Woo Nam , Yong-Jun Kim , Jong-Wook Park , Chi-Sung Oh
IPC分类号： G06F12/14
CPC分类号： G11C11/406 , G11C7/1075 , G11C11/40603 , G11C11/40618
摘要： A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.
摘要翻译：多端口存储器件包括刷新寄存器和刷新控制器，用于防止存储器件的共享存储器单元中的刷新不足。存储装置还包括共享对共享存储器单元的访问的多个端口。刷新寄存器存储关于至少一个刷新命令的信息。刷新控制器根据存储在刷新寄存器中的信息来确定是否在端口权限转换时激活内部刷新操作。

8. 发明授权

US08120980B2 Semiconductor memory device in which a method of controlling a BIT line sense amplifier is improved 有权
标题翻译：提高了控制BIT线读出放大器的方法的半导体存储器件
公开(公告)号：US08120980B2
公开(公告)日：2012-02-21
申请号：US12686561
申请日：2010-01-13
申请人： Chi-Sung Oh , Jung-Bae Lee , Dong-Hyuk Lee
发明人： Chi-Sung Oh , Jung-Bae Lee , Dong-Hyuk Lee
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C5/025 , G11C7/08 , G11C11/4091
摘要： A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.
摘要翻译：半导体存储器件包括读出放大器，读出放大器驱动信号驱动器和控制器。读出放大器被配置为响应于读出放大器驱动信号来检测和放大位线的信号和互补位线的信号。读出放大器驱动信号驱动器包括：第一驱动信号驱动器，被配置为响应于第一读出放大器控制信号经由传输线驱动读出放大器驱动信号;以及第二驱动信号驱动器，被配置为通过传输线驱动读出放大器响应于第二读出放大器控制信号的驱动信号。控制器响应于有效命令激活第一读出放大器控制信号，并且在第一读出放大器控制信号被激活时切换第二读出放大器控制信号。

9. 发明授权

US06724242B2 Pump circuits and methods for integrated circuits including first and second oscillators and first and second pumps 有权
标题翻译：包括第一和第二振荡器以及第一和第二泵的集成电路的泵电路和方法
公开(公告)号：US06724242B2
公开(公告)日：2004-04-20
申请号：US10370398
申请日：2003-02-20
申请人： Hyung-Dong Kim , Chi-Sung Oh
发明人： Hyung-Dong Kim , Chi-Sung Oh
IPC分类号： G05F302
CPC分类号： H02M3/073 , H02M2001/0032 , H02M2003/077 , Y02B70/16
摘要： Boosted voltage generates and methods for an integrated circuit are configured to boost an initial boosted voltage to a first boosted voltage in response to detecting a drop in the initial voltage. The first boosted voltage is then boosted to a second boosted voltage in response to a pulse. The second boosted voltage is then repeatedly boosted to approach the initial boosted voltage in response to an oscillating signal. Accordingly, stable boosted voltages may be generated.
摘要翻译：升压电压产生，并且集成电路的方法被配置为响应于检测到初始电压的下降而将初始升压电压升压到第一升压电压。然后响应于脉冲将第一升压电压升压到第二升压电压。然后响应于振荡信号，第二升压电压被反复升高以接近初始升压电压。因此，可能产生稳定的升压电压。

10. 发明授权

US08929118B2 Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line 有权
标题翻译：具有芯片间连接单元的堆叠存储器件，包括其的存储器系统以及补偿传输线路的延迟时间的方法
公开(公告)号：US08929118B2
公开(公告)日：2015-01-06
申请号：US13080061
申请日：2011-04-05
申请人： Chi-Sung Oh , Jin-Ho Kim , Ho-Cheol Lee , Uk-Song Kang , Hoon Lee
发明人： Chi-Sung Oh , Jin-Ho Kim , Ho-Cheol Lee , Uk-Song Kang , Hoon Lee
IPC分类号： G11C5/06 , G11C5/02 , G11C7/10
CPC分类号： G11C7/10 , G11C5/02 , G11C7/1048
摘要： A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.
摘要翻译：提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号传输线。层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

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