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1. 发明申请

US20140042567A1 MTJ MRAM WITH STUD PATTERNING 有权
标题翻译： MTJ MRAM与STUD PATTERNING
公开(公告)号：US20140042567A1
公开(公告)日：2014-02-13
申请号：US13572197
申请日：2012-08-10
申请人： Dong Ha Jung , Kimihiro Satoh , Jing Zhang , Yuchen Zhou , Yiming Huai
发明人： Dong Ha Jung , Kimihiro Satoh , Jing Zhang , Yuchen Zhou , Yiming Huai
IPC分类号： H01L43/12 , H01L43/02
CPC分类号： H01L43/12 , H01L43/08
摘要： Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase.
摘要翻译：描述了包括螺柱掩模和用于MTJ蚀刻以形成比MTJ柱的其余部分宽的底部电极的可移除间隔套的多层蚀刻掩模的使用。所描述的本发明的第一实施例包括顶部电极和螺柱掩模。在第二和第三实施例中，螺柱掩模是导电材料，并且还用作顶部电极。在形成螺柱掩模之后的实施例中，在其周围形成间隔套，以最初增加蚀刻阶段的掩模宽度。去除间隔物用于进一步蚀刻，以产生逐渐转移到形成MTJ柱的层中的阶梯结构。在一个实施例中，间隔套筒是在蚀刻阶段期间通过净聚合物沉积形成的。

2. 发明授权

US08574928B2 MRAM fabrication method with sidewall cleaning 有权
标题翻译： MRAM制造方法与侧壁清洁
公开(公告)号：US08574928B2
公开(公告)日：2013-11-05
申请号：US13443818
申请日：2012-04-10
申请人： Kimihiro Satoh , Yiming Huai , Yuchen Zhou , Jing Zhang , Dong Ha Jung , Ebrahim Abedifard , Rajiv Yadav Ranjan , Parviz Keshtbod
发明人： Kimihiro Satoh , Yiming Huai , Yuchen Zhou , Jing Zhang , Dong Ha Jung , Ebrahim Abedifard , Rajiv Yadav Ranjan , Parviz Keshtbod
IPC分类号： H01L21/00
CPC分类号： H01L27/222 , H01L43/12
摘要： Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.
摘要翻译：描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。本发明的各种实施方案包括增强或优化方法的方法。如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

3. 发明申请

US20130267042A1 MRAM Fabrication Method with Sidewall Cleaning 有权
标题翻译： MRAM制造方法与侧壁清洁
公开(公告)号：US20130267042A1
公开(公告)日：2013-10-10
申请号：US13443818
申请日：2012-04-10
申请人： Kimihiro Satoh , Yiming Huai , Yuchen Zhou , Jing Zhang , Dong Ha Jung , Ebrahim Abedifard , Rajiv Yadav Ranjan , Parviz Keshtbod
发明人： Kimihiro Satoh , Yiming Huai , Yuchen Zhou , Jing Zhang , Dong Ha Jung , Ebrahim Abedifard , Rajiv Yadav Ranjan , Parviz Keshtbod
IPC分类号： H01L21/02
CPC分类号： H01L27/222 , H01L43/12
摘要： Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.
摘要翻译：描述了用于MRAM的制造方法，其中在互连过程开始之前清洁存储元件柱的侧壁上的任何重新沉积的金属。在实施例中，首先制造柱，然后将介电材料沉积在侧壁上的再沉积金属上的柱上。电介质材料基本上覆盖任何暴露的金属，因此在随后的蚀刻期间减少再沉积的来源。然后进行蚀刻以将电介质材料从顶部电极和柱的侧壁向下移动到至少阻挡层的底部边缘。结果是可能导致在屏障的侧壁上导致电短路的先前重新沉积的金属被去除。本发明的各种实施方案包括增强或优化方法的方法。如所描述的那样，在侧壁被蚀刻清洁之后，进行位线互连处理。

4. 发明授权

US08772888B2 MTJ MRAM with stud patterning 有权
标题翻译： MTJ MRAM螺柱图案
公开(公告)号：US08772888B2
公开(公告)日：2014-07-08
申请号：US13572197
申请日：2012-08-10
申请人： Dong Ha Jung , Kimihiro Satoh , Jing Zhang , Yuchen Zhou , Yiming Huai
发明人： Dong Ha Jung , Kimihiro Satoh , Jing Zhang , Yuchen Zhou , Yiming Huai
IPC分类号： H01L43/00 , H01L43/12
CPC分类号： H01L43/12 , H01L43/08
摘要： Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase.
摘要翻译：描述了包括螺柱掩模和用于MTJ蚀刻以形成比MTJ柱的其余部分宽的底部电极的可移除间隔套的多层蚀刻掩模的使用。所描述的本发明的第一实施例包括顶部电极和螺柱掩模。在第二和第三实施例中，螺柱掩模是导电材料，并且还用作顶部电极。在形成螺柱掩模之后的实施例中，在其周围形成间隔套，以最初增加蚀刻阶段的掩模宽度。去除间隔物用于进一步蚀刻，以产生逐渐转移到形成MTJ柱的层中的阶梯结构。在一个实施例中，间隔套筒是在蚀刻阶段期间通过净聚合物沉积形成的。

5. 发明授权

US08883520B2 Redeposition control in MRAM fabrication process 有权
标题翻译： MRAM制造工艺中的再沉积控制
公开(公告)号：US08883520B2
公开(公告)日：2014-11-11
申请号：US13530381
申请日：2012-06-22
申请人： Kimihiro Satoh , Dong Ha Jung , Ebrahim Abedifard , Parviz Keshtbod , Yiming Huai , Jing Zhang
发明人： Kimihiro Satoh , Dong Ha Jung , Ebrahim Abedifard , Parviz Keshtbod , Yiming Huai , Jing Zhang
IPC分类号： H01L21/00
CPC分类号： H01L43/02 , H01L27/222 , H01L43/12
摘要： Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.
摘要翻译：描述了方法和结构以在柱蚀刻期间减少存储器单元（例如MTJ电池）中的金属沉积材料。一个实施例在位于晶片上暴露的金属表面的电介质层中的着陆焊盘的顶部上形成金属螺柱。另一个实施例分别对MTJ和底部电极进行图案化。底部电极掩模然后覆盖底部电极下面的金属。另一实施例将柱蚀刻工艺分为两个阶段。第一阶段蚀刻到较低的磁性层，然后阻挡层的侧壁被电介质材料覆盖，然后将其垂直蚀刻。蚀刻的第二阶段然后对剩余的层进行图案化。另一个实施例使用顶部电极上方的硬掩模来蚀刻MTJ柱直到靠近底部电极的端点，沉积电介质，然后垂直蚀刻剩余的底部电极。

6. 发明申请

US20130341801A1 Redeposition Control in MRAM Fabrication Process 有权
公开(公告)号：US20130341801A1
公开(公告)日：2013-12-26
申请号：US13530381
申请日：2012-06-22
申请人： Kimihiro Satoh , Dong Ha Jung , Ebrahim Abedifard , Parviz Keshtbod , Yiming Huai , Jing Zhang
发明人： Kimihiro Satoh , Dong Ha Jung , Ebrahim Abedifard , Parviz Keshtbod , Yiming Huai , Jing Zhang
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L43/02 , H01L27/222 , H01L43/12
摘要： Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

7. 发明授权

US09082695B2 Vialess memory structure and method of manufacturing same 有权
标题翻译：无记忆结构及其制造方法
公开(公告)号：US09082695B2
公开(公告)日：2015-07-14
申请号：US13154346
申请日：2011-06-06
申请人： Kimihiro Satoh , Yiming Huai , Jing Zhang
发明人： Kimihiro Satoh , Yiming Huai , Jing Zhang
IPC分类号： H01L29/82 , H01L21/8246 , H01L43/12 , H01L27/115 , H01L27/22 , H01L43/08
CPC分类号： H01L27/222 , H01L27/224 , H01L27/228 , H01L43/08 , H01L43/12
摘要： A method of manufacturing a magnetic memory cell, including a magnetic tunnel junction (MTJ), includes using silicon nitride layer and silicon oxide layer to form a trench for depositing copper to be employed for connecting the MTJ to other circuitry without the use of a via.
摘要翻译：包括磁性隧道结（MTJ）的磁性存储单元的制造方法包括使用氮化硅层和氧化硅层形成用于沉积铜的沟槽，用于将MTJ连接到其它电路而不使用通孔。

8. 发明授权

US08796795B2 MRAM with sidewall protection and method of fabrication 有权
标题翻译： MRAM具有侧壁保护和制造方法
公开(公告)号：US08796795B2
公开(公告)日：2014-08-05
申请号：US13136454
申请日：2011-08-01
申请人： Kimihiro Satoh , Yiming Huai , Jing Zhang , Ebrahim Abedifard
发明人： Kimihiro Satoh , Yiming Huai , Jing Zhang , Ebrahim Abedifard
IPC分类号： H01L27/24 , H01L27/22 , H01L45/00
CPC分类号： H01L27/222 , H01L27/2436 , H01L43/08 , H01L43/12 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.
摘要翻译：描述了BEOL存储器单元，其包括在经由蚀刻互连之前沉积的存储器件（包括例如MTJ元件）上的一个或多个侧壁保护层，以防止在层之间形成电短路。一个实施例使用在存储器件已被图案化之后沉积的单层侧壁保护套管。层材料被垂直地蚀刻以暴露顶部电极的上表面，同时留下围绕存储器件的其余部分的保护材料的残留层。选择保护层的材料以抵抗用于在随后的互连过程中从通孔去除第一介电材料的蚀刻剂。第二实施例使用双层侧壁保护，其中第一层覆盖存储元件优选是无氧电介质，并且第二层在通孔蚀刻期间保护第一层。

9. 发明申请

US20130052752A1 Mram etching processes 有权
标题翻译：摩擦蚀刻工艺
公开(公告)号：US20130052752A1
公开(公告)日：2013-02-28
申请号：US13199490
申请日：2011-08-30
申请人： Kimihiro Satoh , Yiming Huai , Jing Zhang , Rajiv Yadav Ranjan , Parviz Keshtbod , Roger K. Malmhall
发明人： Kimihiro Satoh , Yiming Huai , Jing Zhang , Rajiv Yadav Ranjan , Parviz Keshtbod , Roger K. Malmhall
IPC分类号： H01L21/8246
CPC分类号： H01L43/12 , H01L29/00
摘要： Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.
摘要翻译：本发明的各种实施例涉及用于制造MRAM装置中的MTJ电池的蚀刻工艺。各种实施例可以彼此组合使用。第一实施例在硬掩模和顶电极之间添加硬掩模缓冲层。第二实施例使用多层蚀刻硬掩模。第三实施例使用包括第二层如Ta之下的第一Cu层的多层顶电极结构。第四实施例是用于底部电极去除再沉积材料同时保持更垂直侧壁蚀刻轮廓的两相蚀刻工艺。在第一阶段中，使用碳质反应离子蚀刻去除底部电极层直到端点。在第二阶段中，使用惰性气体和/或氧等离子体去除在先前蚀刻工艺期间沉积的聚合物。

10. 发明申请

US20130032907A1 MRAM with sidewall protection and method of fabrication 有权
公开(公告)号：US20130032907A1
公开(公告)日：2013-02-07
申请号：US13136454
申请日：2011-08-01
申请人： Kimihiro Satoh , Yiming Huai , Jing Zhang , Ebrahim Abedifard
发明人： Kimihiro Satoh , Yiming Huai , Jing Zhang , Ebrahim Abedifard
IPC分类号： H01L29/82 , H01L43/12
CPC分类号： H01L27/222 , H01L27/2436 , H01L43/08 , H01L43/12 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

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