专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06369449B2 Method and apparatus for injection molded flip chip encapsulation 失效
标题翻译：注塑倒装芯片封装的方法和装置
公开(公告)号：US06369449B2
公开(公告)日：2002-04-09
申请号：US09228601
申请日：1999-01-12
申请人： Donald Seton Farquhar , Michael Joseph Klodowski , Kostantinos Papathomas , James Robert Wilcox
发明人： Donald Seton Farquhar , Michael Joseph Klodowski , Kostantinos Papathomas , James Robert Wilcox
IPC分类号： H01L2348
CPC分类号： H01L23/3128 , H01L21/54 , H01L21/563 , H01L23/3121 , H01L24/29 , H01L24/32 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/83104 , H01L2224/92125 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/15151 , H01L2924/15787 , H01L2924/19107 , H01L2924/351 , H01L2924/00 , H01L2924/3512 , H01L2224/05599
摘要： The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.
摘要翻译：由附接到基板的集成电路芯片组成的集成电路芯片组件的电气连接通过将密封剂材料通过基板中的开口分配到集成电路芯片与集成电路芯片之间的空间中而被高粘度密封剂材料封装并增强基质。制造具有加强电互连的集成电路芯片组件，其由于集成电路芯片与集成电路芯片所附接的基板之间的热膨胀系数的差异而产生的应力结果，更能抵抗弱化。

2. 发明授权

US06570261B2 Method and apparatus for injection molded flip chip encapsulation 有权
公开(公告)号：US06570261B2
公开(公告)日：2003-05-27
申请号：US10118395
申请日：2002-04-08
申请人： Donald Seton Farquhar , Michael Joseph Klodowski , Konstantinos Papathomas , James Robert Wilcox
发明人： Donald Seton Farquhar , Michael Joseph Klodowski , Konstantinos Papathomas , James Robert Wilcox
IPC分类号： H01L2348
CPC分类号： H01L23/3128 , H01L21/54 , H01L21/563 , H01L23/3121 , H01L24/29 , H01L24/32 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/83104 , H01L2224/92125 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/15151 , H01L2924/15787 , H01L2924/19107 , H01L2924/351 , H01L2924/00 , H01L2924/3512 , H01L2224/05599
摘要： The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chin assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

3. 发明授权

US5981312A Method for injection molded flip chip encapsulation 失效
标题翻译：注塑倒装芯片封装方法
公开(公告)号：US5981312A
公开(公告)日：1999-11-09
申请号：US884232
申请日：1997-06-27
申请人： Donald Seton Farquhar , Michael Joseph Klodowski , Konstantinos Papathomas , James Robert Wilcox
发明人： Donald Seton Farquhar , Michael Joseph Klodowski , Konstantinos Papathomas , James Robert Wilcox
IPC分类号： H01L21/60 , H01L21/54 , H01L21/56 , H01L23/31 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/3128 , H01L21/54 , H01L21/563 , H01L23/3121 , H01L24/29 , H01L24/32 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/83104 , H01L2224/92125 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/15151 , H01L2924/15787 , H01L2924/19107 , H01L2924/351
摘要： The electrical connections of an integrated circuit chip assembly comprised of an integrated circuit chip attached to a substrate are encapsulated and reinforced with a high viscosity encapsulant material by dispensing the encapsulant material through an opening in the substrate into the space between the integrated circuit chip and the substrate. An integrated circuit chip assembly having a reinforced electrical interconnection which is more resistant to weakening as a result of stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.
摘要翻译：由附接到基板的集成电路芯片组成的集成电路芯片组件的电气连接通过将密封剂材料通过基板中的开口分配到集成电路芯片与集成电路芯片之间的空间中而被高粘度密封剂材料封装并增强基质。制造具有加强电互连的集成电路芯片组件，其由于集成电路芯片与集成电路芯片所附接的基板之间的热膨胀系数的差异而产生的应力结果，更能抵抗弱化。

4. 发明授权

US5847324A High performance electrical cable 失效
标题翻译：高性能电缆
公开(公告)号：US5847324A
公开(公告)日：1998-12-08
申请号：US626732
申请日：1996-04-01
申请人： Donald Seton Farquhar , William Louis Brodsky , Natalie Barbara Feilchenfeld , Lisa Jeanine Jimarez , James Robert Wilcox
发明人： Donald Seton Farquhar , William Louis Brodsky , Natalie Barbara Feilchenfeld , Lisa Jeanine Jimarez , James Robert Wilcox
IPC分类号： H01B7/08 , H05K1/00 , H05K3/28 , H05K3/46
CPC分类号： H05K3/4652 , H01B7/0838 , H01B7/0861 , H05K1/0393 , H05K2201/015 , H05K2201/0154 , H05K3/28 , H05K3/4626 , H05K3/4635 , H05K3/4655 , Y10T29/49124
摘要： A composite cable has a reinforcing layer with conductors disposed on opposed planar surfaces. Dielectric film layers electrically separate the conductors on the planar reinforcing layer from respective layers of additional conductors. The flexible cable is manufactured by laminating a layer of dielectric film and a layer of electrically conductive material onto both sides of a double clad core which provides a strain relief reinforcement for the cable.
摘要翻译：复合电缆具有加强层，导体设置在相对的平面上。介电膜层将平面加强层上的导体与附加导体的相应层电分离。柔性电缆通过将电介质膜和一层导电材料层叠在双包层芯的两侧上来制造，该双层芯提供用于电缆的应变消除加强件。

5. 发明授权

US5993579A High performance electrical cable and method of manufacture 失效
标题翻译：高性能电缆及其制造方法
公开(公告)号：US5993579A
公开(公告)日：1999-11-30
申请号：US876502
申请日：1997-06-16
申请人： Donald Seton Farquhar , William Louis Brodsky , Natalie Barbara Feilchenfeld , Lisa Jeanine Jimarez , James Robert Wilcox
发明人： Donald Seton Farquhar , William Louis Brodsky , Natalie Barbara Feilchenfeld , Lisa Jeanine Jimarez , James Robert Wilcox
IPC分类号： H01B7/08 , H05K1/00 , H05K3/28 , H05K3/46 , H01B13/00
CPC分类号： H05K3/4652 , H01B7/0838 , H01B7/0861 , H05K1/0393 , H05K2201/015 , H05K2201/0154 , H05K3/28 , H05K3/4626 , H05K3/4635 , H05K3/4655 , Y10T29/49124
摘要： A composite cable has a reinforcing layer with conductors disposed on opposed planar surfaces. Dielectric film layers electrically separate the conductors on the planar reinforcing layer from respective layers of additional conductors. The flexible cable is manufactured by laminating a layer of dielectric film and a layer of electrically conductive material onto both sides of a double clad core which provides a strain relief reinforcement for the cable.
摘要翻译：复合电缆具有加强层，导体设置在相对的平面上。介电膜层将平面加强层上的导体与附加导体的相应层电分离。柔性电缆通过将电介质膜和一层导电材料层叠在双包层芯的两侧上来制造，该双层芯提供用于电缆的应变消除加强件。

6. 发明授权

US06094059A Apparatus and method for burn-in/testing of integrated circuit devices 失效
标题翻译：用于集成电路器件的老化/测试的装置和方法
公开(公告)号：US06094059A
公开(公告)日：2000-07-25
申请号：US241045
申请日：1999-02-01
申请人： Jerome A. Frankeny , Anthony P. Ingraham , James Steven Kamperman , James Robert Wilcox
发明人： Jerome A. Frankeny , Anthony P. Ingraham , James Steven Kamperman , James Robert Wilcox
IPC分类号： G01R31/28 , G01R31/02
CPC分类号： G01R31/2886
摘要： A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head. The interposer is positioned between the IC device and the test head, with the contacts on the IC device in contact with the first plurality of connectors and the contact pads on the test head in contact with the second plurality of connectors. Signals are provided to the connector pads from the electrical leads for performing testing and/or burn-in of the integrated circuit device. The testing is performed at elevational temperatures. A test head structure is also disclosed.
摘要翻译：提供了以预定图案布置的在其一个面上具有多个触点的集成电路装置，特别是晶片的测试/应力的技术。提供具有电介质基板和器件接触面和测试器接触面的插入件。设备触点上的第一多个可释放连接器以相同的预定图案布置，并且第二多个可释放连接器以相同的预定图案布置在测试器接触面上。可释放的连接由枝晶形成。导通孔分别连接第一和第二可释放连接器的相应连接器。提供了具有也以相同的预定图案布置的多个接触垫的测试头。在测试头上提供电路以将每个接触焊盘上的每个接触垫连接到外部引线上，以提供与测试头上的每个接触焊盘的信号接触。插入器位于IC器件和测试头之间，IC器件上的触点与第一组多个连接器接触，测试头上的接触焊盘与第二组连接器接触。信号从电引线提供给连接器焊盘，用于执行集成电路器件的测试和/或老化。测试在高温下进行。还公开了测试头结构。

7. 发明授权

US6094060A Test head for applying signals in a burn-in test of an integrated circuit 失效
标题翻译：用于在集成电路的老化测试中应用信号的测试头
公开(公告)号：US6094060A
公开(公告)日：2000-07-25
申请号：US241044
申请日：1999-02-01
申请人： Jerome A. Frankeny , Anthony P. Ingraham , James Steven Kamperman , James Robert Wilcox
发明人： Jerome A. Frankeny , Anthony P. Ingraham , James Steven Kamperman , James Robert Wilcox
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2886
摘要： A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head. The interposer is positioned between the IC device and the test head, with the contacts on the IC device in contact with the first plurality of connectors and the contact pads on the test head in contact with the second plurality of connectors. Signals are provided to the connector pads from the electrical leads for performing testing and/or burn-in of the integrated circuit device. The testing is performed at elevational temperatures. A test head structure is also disclosed.
摘要翻译：提供了以预定图案布置的在其一个面上具有多个触点的集成电路装置，特别是晶片的测试/应力的技术。提供具有电介质基板和器件接触面和测试器接触面的插入件。设备触点上的第一多个可释放连接器以相同的预定图案布置，并且第二多个可释放连接器以相同的预定图案布置在测试器接触面上。可释放的连接由枝晶形成。导通孔分别连接第一和第二可释放连接器的相应连接器。提供了具有也以相同的预定图案布置的多个接触垫的测试头。在测试头上提供电路以将每个接触焊盘上的每个接触垫连接到外部引线上，以提供与测试头上的每个接触焊盘的信号接触。插入器位于IC器件和测试头之间，IC器件上的触点与第一组多个连接器接触，测试头上的接触焊盘与第二组连接器接触。信号从电引线提供给连接器焊盘，用于执行集成电路器件的测试和/或老化。测试在高温下进行。还公开了测试头结构。

8. 发明授权

US5781413A Method and apparatus for directing the input/output connection of integrated circuit chip cube configurations 失效
标题翻译：用于引导集成电路芯片立方体配置的输入/输出连接的方法和装置
公开(公告)号：US5781413A
公开(公告)日：1998-07-14
申请号：US719826
申请日：1996-09-30
申请人： Wayne John Howell , John Steven Kresge , David Brian Stone , James Robert Wilcox
发明人： Wayne John Howell , John Steven Kresge , David Brian Stone , James Robert Wilcox
IPC分类号： H01L21/98 , H01L25/065 , H05K1/11 , H05K1/14 , H05K7/02
CPC分类号： H05K1/141 , H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06596 , H05K1/114 , H05K2201/10378 , H05K2201/10734
摘要： A technique is disclosed for forming a chip cube from a plurality of chips laminated together in front-to-back relationship, the edges of the chip forming a cube face having a set of connectors for each chip thereon. A number "X" of functional chips is required for the operation, and "X+Y" is the number of chips provided in the stack such that there is Y number of chips greater than the number of functional chips required. If any number of chips equal to Y or less are found to be defective, there are enough chips remaining to perform the required function. Thereafter X number of good chips are connected to output circuitry through an interposer. Electrical connectors are provided on all of the IC chips. Contact pads for all of the connectors are provided on one face, and outlet pads are provided on the opposite face of the interposer for at least Y number of outlets. The interposer has vias at least equal to the number of outlet pads. After assembly, the chips are burnt-in, and if there are enough functional chips after burn-in, the interposer is wired to connect X number of sets of chip pads and the outlet pads through the vias. The chip stack is mounted on the interposer wherein all of the connectors on the cube face are connected to all of the chip mounting pads, but only those which have been selected for functioning chips are connected through the vias to the outlet pads.
摘要翻译：公开了一种用于从前后关系层叠在一起的多个芯片形成芯片立方体的技术，芯片的边缘形成具有用于其每个芯片的一组连接器的立方体面。操作需要一个“X”功能芯片，“X + Y”是堆叠中提供的芯片数量，使得Y芯片数量大于所需的功能芯片数量。如果发现任何数量的等于或等于Y的芯片是有缺陷的，则剩余足够的芯片来执行所需的功能。此后，X个好的芯片通过插入器连接到输出电路。所有IC芯片都提供电连接器。用于所有连接器的接触垫设置在一个面上，并且出口垫设置在插入件的相对面上，用于至少Y个出口。插入器具有至少等于插座数量的通孔。组装之后，芯片烧坏，如果老化后有足够的功能芯片，则插入器通过通孔连接X个芯片组和出口焊盘。芯片堆叠安装在插入器上，其中立方体表面上的所有连接器都连接到所有的芯片安装焊盘，但只有那些已被选择用于功能芯片的连接器通过通孔连接到出口焊盘。

9. 发明授权

US5659951A Method for making printed circuit board with flush surface lands 失效
标题翻译：制造具有齐平表面焊盘的印刷电路板的方法
公开(公告)号：US5659951A
公开(公告)日：1997-08-26
申请号：US632232
申请日：1996-04-15
申请人： Thomas Patrick Gall , David Brian Stone , Russell Thomas White, Jr. , James Robert Wilcox
发明人： Thomas Patrick Gall , David Brian Stone , Russell Thomas White, Jr. , James Robert Wilcox
IPC分类号： H05K1/11 , H05K1/14 , H05K3/18 , H05K3/42 , H05K3/36
CPC分类号： H05K1/116 , H05K1/144 , H05K3/426 , H05K2201/0376 , H05K2201/09036 , H05K3/181 , H05K3/429 , Y10T29/49124 , Y10T29/49126 , Y10T29/49165
摘要： A method for making a printed circuit board with a flush surface land begins by forming a multi-layer printed circuit board with a recess in a surface dielectric layer. Then, a hole is drilled into or through the printed circuit board; the hole communicates with the recess. After the recess is formed, a conductive material is provided in the recess to form a surface land and provided on an inner surface of the hole to form a plated hole which is electrically connected to the surface land. The conductive material in the recess has a thickness substantially equal to a depth of the recess such that the surface land is flush with an adjacent surface of the dielectric surface layer.
摘要翻译：通过在表面电介质层中形成具有凹部的多层印刷电路板，来制造具有平坦表面的印刷电路板的方法。然后，在印刷电路板中穿过或穿过孔; 孔与凹部连通。在形成凹部之后，在凹部中设置导电材料以形成表面焊盘并且设置在孔的内表面上以形成电连接到表面焊盘的电镀孔。凹部中的导电材料的厚度基本上等于凹部的深度，使得表面焊盘与电介质表面层的相邻表面齐平。

10. 发明授权

US5949246A Test head for applying signals in a burn-in test of an integrated circuit 失效
公开(公告)号：US5949246A
公开(公告)日：1999-09-07
申请号：US789926
申请日：1997-01-28
申请人： Jerome A. Frankeny , Anthony P. Ingraham , James Steven Kamperman , James Robert Wilcox
发明人： Jerome A. Frankeny , Anthony P. Ingraham , James Steven Kamperman , James Robert Wilcox
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2886
摘要： A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head. The interposer is positioned between the IC device and the test head, with the contacts on the IC device in contact with the first plurality of connectors and the contact pads on the test head in contact with the second plurality of connectors. Signals are provided to the connector pads from the electrical leads for performing testing and/or burn-in of the integrated circuit device. The testing is performed at elevational temperatures. A test head structure is also disclosed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式