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1. 发明授权

US06843929B1 Accelerated etching of chromium 失效
标题翻译：加速蚀刻铬
公开(公告)号：US06843929B1
公开(公告)日：2005-01-18
申请号：US09514526
申请日：2000-02-28
申请人： Donald S. Farquhar , Edmond O. Fey , Elizabeth Foster , Michael J. Klodowski , Paul G. Rickerl
发明人： Donald S. Farquhar , Edmond O. Fey , Elizabeth Foster , Michael J. Klodowski , Paul G. Rickerl
IPC分类号： C23F1/26 , H01L21/3213 , B44C1/22
CPC分类号： H01L21/32134 , C23F1/26
摘要： A method and associated structure for increasing the rate at which a chromium volume is etched when the chromium body is contacted by an acid solution such as hydrochloric acid. The etch rate is increased by a metallic or steel body in continuous electrical contact with the chromium volume, both of which are in continuous contact with the acid solution. At a temperature between about 21° C. and about 52° C., and a hydrochloric acid concentration (molarity) between about 1.2 M and about 2.4 M, the etch rate is at least a factor of about two greater than an etch rate that would occur in an absence of the steel body. In one embodiment, the chromium volume is a chromium layer that rests upon a conductive layer that includes a metal such as copper, wherein the acid solution is not in contact with the conductive layer. In another embodiment, the chromium volume is a chromium layer located under a conductive layer that includes a metal such as copper, wherein the steel body and the acid solution both contact the chromium layer through an opening in the conductive layer such that the opening exposes the chromium layer.
摘要翻译：一种用于提高当铬体与诸如盐酸的酸溶液接触时铬体积被蚀刻的速率的方法和相关结构。蚀刻速率由与铬体积连续电接触的金属或钢体增加，两者都与酸溶液连续接触。在约21℃至约52℃的温度和约1.2M至约2.4M之间的盐酸浓度（摩尔浓度）之间，蚀刻速率至少比蚀刻速率大约两倍，将在没有钢体的情况下发生。在一个实施方案中，铬体积是沉积在包括诸如铜的金属的导电层上的铬层，其中酸溶液不与导电层接触。在另一个实施方案中，铬体积是位于导电层下方的铬层，该层包括诸如铜的金属，其中钢体和酸溶液都通过导电层中的开口接触铬层，使得开口暴露于铬层。

2. 发明授权

US06829823B2 Method of making a multi-layered interconnect structure 有权
标题翻译：制造多层互连结构的方法
公开(公告)号：US06829823B2
公开(公告)日：2004-12-14
申请号：US10067551
申请日：2002-02-05
申请人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
发明人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
IPC分类号： H01K310
CPC分类号： H05K3/4641 , H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/12044 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： A method of making a multi-layered interconnect structure. First and second electrically conductive members are formed on the first and second dielectric layers, respectively. The dielectric layer are formed on opposing surfaces of a thermally conductive layer. A first and second electrically conductive layer is formed within the first dielectric layer. The second electrically conductive layer includes shielded signal conductors and is positioned between the first electrically conductive layer and the thermally conductive layer. A plated through hole (PTH) formed through the interconnect structure is electrically connected to one of the first and second electrically conductive members and to one of the shielded signal conductors. A third dielectric layer, formed on the first dielectric layer and on portions of the first electrically conductive members, substantially overlies the PTH and includes a high density interconnect layer for providing an electrical path from an electronic device to the shielded signal conductors.
摘要翻译：一种制造多层互连结构的方法。第一和第二导电构件分别形成在第一和第二电介质层上。电介质层形成在导热层的相对表面上。第一和第二导电层形成在第一介电层内。第二导电层包括屏蔽信号导体并且位于第一导电层和导热层之间。通过互连结构形成的电镀通孔（PTH）电连接到第一和第二导电构件中的一个和屏蔽信号导体之一。形成在第一介电层上和第一导电构件的部分上的第三电介质层基本上覆盖在PTH上，并且包括用于提供从电子器件到屏蔽信号导体的电气路径的高密度互连层。

3. 发明授权

US06373717B1 Electronic package with high density interconnect layer 有权
公开(公告)号：US06373717B1
公开(公告)日：2002-04-16
申请号：US09540172
申请日：2000-03-31
申请人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
发明人： Francis J. Downes, Jr. , Donald S. Farquhar , Elizabeth Foster , Robert M. Japp , Gerald W. Jones , John S. Kresge , Robert D. Sebesta , David B. Stone , James R. Wilcox
IPC分类号： H05K118
CPC分类号： H05K3/4641 , H01L21/4853 , H01L23/3735 , H01L23/49822 , H01L2224/16225 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01046 , H01L2924/01068 , H01L2924/01078 , H01L2924/01322 , H01L2924/12044 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/114 , H05K3/429 , H05K3/4602 , H05K3/4608 , H05K3/4623 , H05K3/4626 , H05K3/4632 , H05K3/4688 , H05K2201/0141 , H05K2201/0191 , H05K2201/068 , H05K2201/09509 , H05K2201/09536 , H05K2201/09554 , H05K2201/0959 , H05K2201/096 , H05K2201/10378 , Y10T29/49155 , Y10T29/49165 , H01L2224/0401
摘要： An electronic package, and method of making the electronic package, is provided. The package includes a semiconductor chip and an multi-layered interconnect structure having a high density interconnect layer such as an allylated surface layer. The semiconductor chip includes a plurality of contact members on one of its surfaces that are connected to the multi-layered interconnect structure by a plurality of solder connections. The multi-layered interconnect structure is adapted for electrically interconnecting the semiconductor chip to a circuitized substrate (eg., circuit board) with another plurality of solder connections and includes a thermally conductive layer being comprised of a material having a selected thickness and coefficient of thermal expansion to substantially prevent failure of the solder connections between said first plurality of electrically conductive members and the semiconductor chip. The electronic package further includes a dielectric material having an effective modulus to assure sufficient compliancy of the multi-layered interconnect structure during operation. The allylated surface layer has the property of being able to withstand thermal stresses that arise during thermal cycling operation of the electronic package.

4. 发明授权

US07063762B2 Circuitized substrate and method of making same 失效
公开(公告)号：US07063762B2
公开(公告)日：2006-06-20
申请号：US10643909
申请日：2003-08-20
申请人： Elizabeth Foster , Gregory Kevern , Anita Sargent
发明人： Elizabeth Foster , Gregory Kevern , Anita Sargent
IPC分类号： H05K3/38
CPC分类号： H01L23/49894 , H01L21/4846 , H01L2924/0002 , H05K1/034 , H05K3/181 , H05K3/188 , H05K2201/015 , H05K2201/0329 , Y10S428/901 , Y10T428/24917 , H01L2924/00
摘要： A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.

5. 发明授权

US06835533B2 Photoimageable dielectric epoxy resin system film 失效
标题翻译：可光成像介电环氧树脂体系膜
公开(公告)号：US06835533B2
公开(公告)日：2004-12-28
申请号：US10781073
申请日：2004-02-18
申请人： Elizabeth Foster , Gary A. Johansson , Heike Marcello , David J. Russell
发明人： Elizabeth Foster , Gary A. Johansson , Heike Marcello , David J. Russell
IPC分类号： G03F7038
CPC分类号： G03F7/0385 , G03F7/038 , H05K3/0023 , H05K3/4644 , H05K3/4676 , Y10T428/24851
摘要： A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110° C. A photoimageable dielectric film is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier; from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20° C.) comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0% to about 5% solvent; applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.
摘要翻译：一种制造电路化基板的方法，其减少短路，并且不需要烘烤和得到的膜。该方法使用溶剂含量小于约5％的光致成像电介质膜，当固化时玻璃化转变温度大于约110℃。提供具有约95％至约100的光致成像电介质膜％固体，并且包含：0％至约30％的固体，颗粒状流变改性剂; 约70％至约100％的环氧树脂体系的固体（20℃的液体），包含：约85％至约99.9％的环氧树脂; 和约0.1至15份的总树脂重量，阳离子光引发剂; 0％至约5％的溶剂; 将光致成像电介质膜施加到电路化基板上; 并将膜暴露于光化辐射。

6. 发明授权

US06706464B2 Method of fabricating circuitized structures 失效
标题翻译：制造电路结构的方法
公开(公告)号：US06706464B2
公开(公告)日：2004-03-16
申请号：US10345561
申请日：2003-01-16
申请人： Elizabeth Foster , Gary A. Johansson , Heike Marcello , David J. Russell
发明人： Elizabeth Foster , Gary A. Johansson , Heike Marcello , David J. Russell
IPC分类号： G03F740
CPC分类号： G03F7/0385 , G03F7/038 , H05K3/0023 , H05K3/4644 , H05K3/4676 , Y10T428/24851
摘要： A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110° C. A photoimageable dielectric film, is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier, from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20° C. comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0 to about 5% solvent, applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.
摘要翻译：一种制造电路化基板的方法，其减少短路，并且不需要烘烤和得到的膜。该方法采用溶剂含量小于约5％的光致成像电介质膜，当固化时玻璃化转变温度大于约110℃。提供了可见光电介质膜，其具有约95％至约 100％固体，并且包含：固体的0％至约30％的颗粒状流变改性剂，约70％至约100％的环氧树脂体系的固体（液体在20℃，包括：来自约85％至约99.9％的环氧树脂;和约0.1至15份的总树脂重量，阳离子光引发剂; 0至约5％的溶剂，将可光成像的电介质膜施加到电路化基板;以及将膜暴露于光化辐射。

7. 发明授权

US08838543B2 Archiving system that facilitates systematic cataloguing of archived documents for searching and management 有权
标题翻译：归档系统，便于系统编目归档文件进行搜索和管理
公开(公告)号：US08838543B2
公开(公告)日：2014-09-16
申请号：US12927693
申请日：2010-11-19
申请人： Gabrielle Sarah Phyo , Nickola John Vidovich , Elizabeth Foster
发明人： Gabrielle Sarah Phyo , Nickola John Vidovich , Elizabeth Foster
IPC分类号： G06F17/00 , G06Q10/00 , G06F17/30
CPC分类号： G06F17/30011 , G06Q10/00
摘要： An archiving system for enabling searching for collections of items is disclosed. A processing unit displays an archived items collection management template in respect of a particular collection of items and prompts a user to complete the template fields with data obtained by the user from manually reviewing that collection of items to capture information relevant to each of the template fields. An archiving controller stores, in pre-determined data fields of a storage area of a data store corresponding to said collection of items, the data from the completed template fields. A document search controller may search the pre-determined data fields of the storage areas of the data store corresponding to each of the collections of items to identify ones of the collection of items which match search criteria.
摘要翻译：公开了一种用于搜索项目集合的归档系统。处理单元针对特定的项目集合显示归档项集合管理模板，并且提示用户使用用户获得的数据来完成模板字段，从而手动查看项目集合以捕获与每个模板字段相关的信息。存档控制器在对应于所述项目集合的数据存储的存储区域的预定数据字段中存储来自完成的模板字段的数据。文档搜索控制器可以搜索与每个项目集合相对应的数据存储区域的存储区域的预定数据字段，以识别符合搜索条件的项目集合中的那些。

8. 发明授权

US07084509B2 Electronic package with filled blinds vias 有权
标题翻译：带盲孔通孔的电子包装
公开(公告)号：US07084509B2
公开(公告)日：2006-08-01
申请号：US10263909
申请日：2002-10-03
申请人： Frank D. Egitto , Elizabeth Foster , Raymond T. Galasco , Voya R. Markovich , Manh-Quan Tam Nguyen
发明人： Frank D. Egitto , Elizabeth Foster , Raymond T. Galasco , Voya R. Markovich , Manh-Quan Tam Nguyen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K1/115 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K3/4602 , H05K2201/09509 , H05K2201/09554 , H05K2201/096 , H05K2203/0733 , H01L2924/00
摘要： The density of electronic packaging and the electrical reliability of the sub-assemblies utilizing stacked blind vias are improved by providing a blind, landless via in a first dielectric layer laminated to a conductive metal core serving as a ground plane or a power plane. A hole is provided through the dielectric layer extending to the core. A metal, such as copper, is deposited electrolytically using the metal core as the cathode, or electrolessly without seeding into the hole. The metal is deposited on the core and progressively builds in the hole to the depth required for the via. A second dielectric layer is laminated to the first, and is provided with a second layer blind via aligned with the first via. This second via may be formed by conventional plating techniques. Multiple dielectric layers with stacked blind vias can be assembled in this manner.
摘要翻译：通过在层叠到用作接地平面或电源平面的导电金属芯的第一介电层中提供盲目的无地通孔来改善电子封装的密度和利用堆叠盲孔的子组件的电可靠性。通过延伸到芯的电介质层提供孔。使用金属芯作为阴极电解沉积诸如铜的金属，或者无电渗入孔中。金属沉积在芯上并逐渐建立在孔中以达到通孔所需的深度。第二电介质层被层压到第一电介质层，并且具有与第一通孔对准的第二层盲孔。该第二通孔可以由常规电镀技术形成。可以以这种方式组装具有堆叠的盲孔的多个电介质层。

9. 发明授权

US06528218B1 Method of fabricating circuitized structures 失效
标题翻译：制造电路结构的方法
公开(公告)号：US06528218B1
公开(公告)日：2003-03-04
申请号：US09808334
申请日：2001-03-14
申请人： Elizabeth Foster , Gary A. Johansson , Heike Marcello , David J. Russell
发明人： Elizabeth Foster , Gary A. Johansson , Heike Marcello , David J. Russell
IPC分类号： G03F711
CPC分类号： G03F7/0385 , G03F7/038 , H05K3/0023 , H05K3/4644 , H05K3/4676 , Y10T428/24851
摘要： A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110° C. A photoimageable dielectric film is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier; from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20° C.) comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0 to about 5% solvent; applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.
摘要翻译：一种制造电路化基板的方法，其减少短路，并且不需要烘烤和得到的膜。该方法使用溶剂含量小于约5％的光致成像电介质膜，当固化时玻璃化转变温度大于约110℃。提供具有约95％至约100的光致成像电介质膜％固体，并且包含：0％至约30％的固体，颗粒状流变改性剂; 约70％至约100％的环氧树脂体系的固体（20℃的液体），包含：约85％至约99.9％的环氧树脂; 和约0.1至15份的总树脂重量，阳离子光引发剂; 0至约5％的溶剂; 将光致成像电介质膜施加到电路化基板上; 并将膜暴露于光化辐射。

10. 发明授权

US5874154A Structure including a partially electrochemically reduced halogenated polymeric containing layer and an electrically conductive pattern 失效
标题翻译：包括部分电化学还原的卤化聚合物包含层和导电图案的结构
公开(公告)号：US5874154A
公开(公告)日：1999-02-23
申请号：US711865
申请日：1996-09-12
申请人： Harry Randall Bickford , Peter J. Duke , Elizabeth Foster , Martin Goldberg , Voya Rista Markovich , Linda Matthew , Donald G. McBride , Terrence Robert O'Toole , Stephen Leo Tisdale , Alfred Viehbeck
发明人： Harry Randall Bickford , Peter J. Duke , Elizabeth Foster , Martin Goldberg , Voya Rista Markovich , Linda Matthew , Donald G. McBride , Terrence Robert O'Toole , Stephen Leo Tisdale , Alfred Viehbeck
IPC分类号： C08J3/24 , C23C18/20 , C23C18/28 , C25D5/56 , H05K1/03 , H05K3/18 , H05K3/38 , H05K3/42 , B32B3/24 , B32B15/08
CPC分类号： H05K3/422 , C23C18/208 , C23C18/2093 , C23C18/30 , C25D5/56 , H05K3/381 , H05K1/034 , H05K3/181 , Y10S428/901 , Y10T428/24273 , Y10T428/24322 , Y10T428/24339 , Y10T428/24802 , Y10T428/3154 , Y10T428/31544 , Y10T428/31678
摘要： A structure including a halogenated polymeric-containing layer. At least a portion of a surface of the halogenated polymeric-containing layer is electrochemically reduced. An electrically conductive pattern is provided over at least a portion of the electrochemically reduced portion of the halogenated polymeric-containing layer.
摘要翻译：包含含卤代聚合物层的结构。含卤化聚合物层的至少一部分表面被电化学还原。在含卤化聚合物层的电化学还原部分的至少一部分上提供导电图案。

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