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    • 1. 发明授权
    • Programmable logic array adder
    • 可编程逻辑阵列加法器
    • US4157590A
    • 1979-06-05
    • US866689
    • 1978-01-03
    • Donald G. GriceDavid F. JohnsonArnold Weinberger
    • Donald G. GriceDavid F. JohnsonArnold Weinberger
    • G06F7/50G06F7/505G06F7/508
    • G06F7/5057
    • This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two bit decoder for receiving each like order pairs of digits A.sub.i, B.sub.i of two n digit binary numbers A.sub.0, A.sub.1....A.sub.n-1 and B.sub.0, B.sub.1....B.sub.n-1 plus a carry C.sub.in. The decoders generate an output signal called a min term on a different line for each of the four possible combinations A.sub.i B.sub.i, A.sub.i B.sub.i, A.sub.i B.sub.i and A.sub.i B.sub.i of the true and complement of each pair. The min terms from the decoders are fed to an array called the product term generator or AND array which generates product termsf.sub.p =f.sub.0 (A.sub.0,B.sub.0) f.sub.1 (A.sub.1,B.sub.1)....f.sub.n-1 (A.sub.n-1, B.sub.n-1) f.sub.n (C.sub.in)The product terms are fed to a second array called a sum of product term generator or OR array that sums product terms f.sub.p. A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an AND function to generate a sum bit S.sub.i that is an AND of two functions supplied by the OR array to the inputs of the latches to generate a sum S.sub.0, S.sub.1....S.sub.n-1 plus a carry C.sub.out for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an AND function.
    • 本说明书公开了一种实现在可编程逻辑阵列(PLA)中的多位二进制加法器。 这里使用的特定可编程逻辑阵列具有单独的两位解码器,用于接收每个类似的两个n位二进制数A0,A1 ...的数字A 1,B 1,A 1和B 0,B 1 .... B n- 1加一个进位Cin。 解码器为每对的真和补的四个可能组合AiBi,AiBi,AiBi和AiBi中的每一个生成称为最小项的输出信号。 来自解码器的最小项被馈送到称为产品项发生器或AND阵列的阵列,其产生乘积项FP = F0(A0,B0)f1(A1,B1)... fn-1(An-1,Bn -1)fn(Cin)将产品条款馈送到称为产品项生成器或OR数组的和的第二个数组,其与产品项fp相加。 一系列锁存器是构成解放军的逻辑元件的序列。 这些锁存器各自执行AND功能,以产生和位Si,它是OR阵列提供给两个功能的AND的锁存器的输入,以产生一个和S0,S1 ....Sn-1加一个进位Cout, 解放军输出的加法器。 该加法器针对具有执行AND功能的锁存器的PLA进行了优化。
    • 4. 发明授权
    • Process for continuous thermosol dyeing of textile fabrics
    • 纺织品连续热熔染染工艺
    • US4448582A
    • 1984-05-15
    • US344405
    • 1982-02-01
    • David F. Johnson
    • David F. Johnson
    • D06B19/00D06C7/02D06B5/08D06B21/00
    • D06B19/0011D06C7/02Y10S8/933
    • A textile fabric formed of synthetic fibrous material or blends with natural fibers to which dyestuffs have been applied is subjected to a thermosol heat treatment by directing the fabric supported on an air permeable conveyor through a heated oven while directing heated air downwardly through the fabric and through the underlying supporting conveyor and while at predetermined longitudinally spaced locations as the fabric travels through the oven directing heated air upwardly through the open mesh conveyor and into contact with the fabric so as to lift portions of the fabric from the conveyor to permit free shrinkage and bulking of the fabric while avoiding distortion of the fabric or obtaining an undesirable ironed surface appearance as would occur if the fabric were pinned to the conveyor. This method also achieves very rapid and efficient heat transfer to the fabric and thus avoids the extreme time and temperature conditions which result in harsh treatment of the fabric.
    • 由合成纤维材料或与已经施加染料的天然纤维的混合物形成的纺织织物经受热溶胶热处理,通过将支撑在透气的输送机上的织物引导通过加热的烘箱,同时将加热的空气向下通过织物并通过 底部的支撑输送机,同时在织物行进通过烘箱的预定的纵向间隔位置处,同时将加热的空气向上引导通过打开的网状输送机并与织物接触,从而将织物的部分从输送机提升以允许自由收缩和膨胀 的织物,同时避免织物变形或获得不希望的熨烫表面外观,如果织物被钉扎在输送机上将会发生。 该方法还实现了对织物的非常快速和有效的热传递,从而避免了导致织物严酷处理的极端时间和温度条件。