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1. 发明授权

US5636133A Efficient generation of fill shapes for chips and packages 失效
标题翻译：有效地生成芯片和封装的填充形状
公开(公告)号：US5636133A
公开(公告)日：1997-06-03
申请号：US445447
申请日：1995-05-19
申请人： Donald G. Chesebro , Young O. Kim , Mark A. Lavin , Daniel N. Maynard
发明人： Donald G. Chesebro , Young O. Kim , Mark A. Lavin , Daniel N. Maynard
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An efficient method for modifying a chip or package design allows for the creation of small shapes without excessive expansion of design data. A computer program takes a physical design, represented in a computer data file, and generates a modified version of the design in which fill shapes have been added. Subsequently, when the modified design is processed, the resulting semiconductor chip or package will contain physical images of the added fill shapes, with the effect of making local pattern density more uniform and hence reducing process-induced variations in feature size and shape.
摘要翻译：修改芯片或封装设计的有效方法允许创建小形状而不会过度扩展设计数据。计算机程序采用计算机数据文件中的物理设计，并生成已添加填充形状的设计的修改版本。随后，当改进的设计被处理时，所得到的半导体芯片或封装将包含所添加的填充形状的物理图像，具有使局部图案密度更均匀并因此减少特征尺寸和形状的工艺引起的变化的效果。

2. 发明申请

US20080232675A1 SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS 失效
标题翻译：集成电路系统缺陷的搜索与分析系统
公开(公告)号：US20080232675A1
公开(公告)日：2008-09-25
申请号：US12132710
申请日：2008-06-04
申请人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

3. 发明授权

US07404174B2 method for generating a set of test patterns for an optical proximity correction algorithm 有权
标题翻译：用于生成用于光学邻近校正算法的一组测试图案的方法
公开(公告)号：US07404174B2
公开(公告)日：2008-07-22
申请号：US10710648
申请日：2004-07-27
申请人： David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.
摘要翻译：一种合成布局图案以测试光学邻近校正算法的方法。该方法包括以下步骤：在一组沃尔什模式矩阵中体现沃尔什模式; 从所述一组沃尔什图案矩阵中处理矩阵组以形成一组测试矩阵; 将测试矩阵的集合映射到测试模式集合。

4. 发明申请

US20080247633A1 SYSTEM FOR GENERATING A SET OF TEST PATTERNS FOR AN OPTICAL PROXIMITY CORRECTION ALGORITHM 审中-公开
标题翻译：用于生成一组用于光临近度校正算法的测试模式的系统
公开(公告)号：US20080247633A1
公开(公告)日：2008-10-09
申请号：US12117934
申请日：2008-05-09
申请人： David L DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： David L DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06K9/00
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A system of synthesizing layout patterns to test an optical proximity correction algorithm. The method comprises the steps of: embodying Walsh patterns in a set of Walsh pattern matrices; processing groups of matrices from the set of Walsh pattern matrices to form a set of test matrices; mapping the set of test matrices to a test pattern set.
摘要翻译：一种合成布局图案以测试光学邻近校正算法的系统。该方法包括以下步骤：在一组沃尔什模式矩阵中体现沃尔什模式; 从所述一组沃尔什图案矩阵中处理矩阵组以形成一组测试矩阵; 将测试矩阵的集合映射到测试模式集合。

5. 发明授权

US07415695B2 System for search and analysis of systematic defects in integrated circuits 有权
标题翻译：集成电路系统缺陷的搜索和分析系统
公开(公告)号：US07415695B2
公开(公告)日：2008-08-19
申请号：US11748575
申请日：2007-05-15
申请人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

6. 发明授权

US06738954B1 Method for prediction random defect yields of integrated circuits with accuracy and computation time controls 有权
标题翻译：用于精确计算时间控制的集成电路预测随机缺陷产量的方法
公开(公告)号：US06738954B1
公开(公告)日：2004-05-18
申请号：US09636478
申请日：2000-08-10
申请人： Archibald J. Allen , Wilm E. Donath , Alan D. Dziedzic , Mark A. Lavin , Daniel N. Maynard , Dennis M. Newns , Gustavo E. Tellez
发明人： Archibald J. Allen , Wilm E. Donath , Alan D. Dziedzic , Mark A. Lavin , Daniel N. Maynard , Dennis M. Newns , Gustavo E. Tellez
IPC分类号： G06F1750
CPC分类号： H01L22/20 , G01R31/31705
摘要： A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.
摘要翻译：一种计算具有装置形状的集成电路的制造成品率的方法包括将集成电路分为故障机构细分（每个故障机构细分包括一个或多个故障机制，并且每个故障机制包括一个或多个缺陷机构），将故障机制细分为每个区域的分区，预处理每个分区中的设备形状，通过对每个分区的每个故障机制和每个分区的平均故障概率的数值积分计算每个故障机制的初始平均故障数故障机制（数值积分产生每个缺陷机制的缺陷尺寸列表，初始平均值的计算包括设置最大积分误差极限，每个缺陷尺寸的总体最大样本量，每个故障的可允许故障mechansim），并计算最终的平均数fau 通过迭代地减少每个故障机制的初始平均故障数量的统计误差，直到统计误差低于误差极限为止，用于集成电路。

7. 发明授权

US07552417B2 System for search and analysis of systematic defects in integrated circuits 失效
标题翻译：集成电路系统缺陷的搜索和分析系统
公开(公告)号：US07552417B2
公开(公告)日：2009-06-23
申请号：US12132710
申请日：2008-06-04
申请人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. The invention first performs a preliminary extracting and index processing of the circuit design and then performs feature searching. When performing the preliminary extracting and index processing the invention establishes a window grid for the circuit design and merges basis patterns with shapes in the circuit design within each window of the window grid. The invention transforms shapes in a each window into feature vectors by finding intersections between the basis patterns and the shapes in the windows. Then, the invention clusters the feature vectors to produce an index of feature vectors. After performing the extracting and index processing, the invention performs the process of feature searching by first identifying a defect region window of the circuit layout and similarly merging basis patterns with shapes in the defect region window. This merging process can include rotating and mirroring the shapes in the defect region. The invention similarly transforms shapes in the defect region window into defect vectors by finding intersections between basis patterns and the shapes in the defect region. Then, the invention can easily find feature vectors that are similar to the defect vector using, for example, representative feature vectors from the index of feature vectors. Then, the similarities and differences between the defect vectors and the feature vectors can be analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。本发明首先进行电路设计的初步提取和索引处理，然后执行特征搜索。当执行初步提取和索引处理时，本发明建立了用于电路设计的窗口网格，并且将窗体网格的每个窗口内的电路设计中的形状与基本图案合并。本发明通过在窗口中找到基本图案和形状之间的交点来将每个窗口中的形状转换为特征向量。然后，本发明聚集特征向量以产生特征向量的索引。在执行提取和索引处理之后，本发明通过首先识别电路布局的缺陷区域窗口并且将基本模式与缺陷区域窗口中的形状类似地合并来执行特征搜索的处理。该合并过程可以包括旋转和镜像缺陷区域中的形状。本发明类似地通过在缺陷区域中找到基础图案和形状之间的交点来将缺陷区域窗口中的形状转换为缺陷向量。然后，本发明可以使用例如来自特征向量的索引的代表性特征向量容易地找到与缺陷向量相似的特征向量。然后，可以分析缺陷向量和特征向量之间的相似性和差异。

8. 发明授权

US07284230B2 System for search and analysis of systematic defects in integrated circuits 有权
标题翻译：集成电路系统缺陷的搜索和分析系统
公开(公告)号：US07284230B2
公开(公告)日：2007-10-16
申请号：US10605849
申请日：2003-10-30
申请人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
发明人： Bette L. Bergman Reuter , David L. DeMaris , Mark A. Lavin , William C. Leipold , Daniel N. Maynard , Maharaj Mukherjee
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Disclosed is a method of locating systematic defects in integrated circuits. Extracting and index processing of a circuit design and feature searching are performed. During extracting and index processing, a window grid for the circuit design is established and basis patterns are merged with shapes within each. Shapes in each window are transformed into feature vectors by finding intersections between basis patterns and shapes. Feature vectors are clustered to produce an index of feature vectors. During feature searching, a defect region window of the circuit layout is identified and basis patterns are merged with shapes in the defect region window. Shapes in the defect region window are transformed into defect vectors by finding intersections between basis patterns and shapes. Feature vectors similar to the defect vector are found using representative feature vectors from the index of feature vectors. Similarities and differences between defect vectors and feature vectors are analyzed.
摘要翻译：公开了一种定位集成电路系统缺陷的方法。执行电路设计和特征搜索的提取和索引处理。在提取和索引处理期间，建立了用于电路设计的窗口网格，并且将基本图案与每个窗体中的形状合并。通过查找基础图案和形状之间的交点，将每个窗口中的形状转换为特征向量。将特征向量聚类以产生特征向量的索引。在特征搜索期间，识别电路布局的缺陷区域窗口，并将基本图案与缺陷区域窗口中的形状合并。通过发现基础图案和形状之间的交点，将缺陷区域窗口中的形状转换为缺陷向量。使用来自特征向量索引的代表特征向量，找到与缺陷向量相似的特征向量。分析缺陷向量和特征向量之间的相似性和差异性。

9. 发明授权

US07893468B2 Optical sensor including stacked photodiodes 有权
标题翻译：光学传感器包括堆叠的光电二极管
公开(公告)号：US07893468B2
公开(公告)日：2011-02-22
申请号：US12129716
申请日：2008-05-30
申请人： Jeffrey P. Gambino , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel , Raymond J. Rosner
发明人： Jeffrey P. Gambino , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel , Raymond J. Rosner
IPC分类号： H01L29/72
CPC分类号： H01L27/14647 , H01L27/14632 , H01L27/14641 , H01L27/14687
摘要： A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes.
摘要翻译：互补金属氧化物半导体（CMOS）图像传感器包括在第一半导体衬底中形成包括第一半导体材料的第一感光二极管。在第二半导体衬底中形成包括具有与第一半导体材料不同的光检测波长范围的第二半导体材料的第二光敏二极管。用于保持和检测包括CMOS图像传感器的感测电路的电荷的半导体器件也可以形成在第二半导体衬底中。第一半导体衬底和第二半导体衬底被接合，使得第一感光二极管位于第二感光二极管的下方。第一和第二光敏二极管的垂直堆叠检测第一和第二半导体材料的组合检测波长范围内的光。感测装置可以在第一和第二光敏二极管之间共享。

10. 发明授权

US07883916B2 Optical sensor including stacked photosensitive diodes 有权
标题翻译：光学传感器包括堆叠感光二极管
公开(公告)号：US07883916B2
公开(公告)日：2011-02-08
申请号：US12129714
申请日：2008-05-30
申请人： Jeffrey P. Gambino , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel , Raymond J. Rosner
发明人： Jeffrey P. Gambino , Daniel N. Maynard , Kevin N. Ogg , Richard J. Rassel , Raymond J. Rosner
IPC分类号： H01L21/00
CPC分类号： H01L27/14647 , H01L27/14609 , H01L27/14641 , H01L27/14683
摘要： A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes.
摘要翻译：互补金属氧化物半导体（CMOS）图像传感器包括在第一半导体衬底中形成包括第一半导体材料的第一感光二极管。在第二半导体衬底中形成包括具有与第一半导体材料不同的光检测波长范围的第二半导体材料的第二光敏二极管。用于保持和检测包括CMOS图像传感器的感测电路的电荷的半导体器件也可以形成在第二半导体衬底中。第一半导体衬底和第二半导体衬底被接合，使得第一感光二极管位于第二感光二极管的下方。第一和第二光敏二极管的垂直堆叠检测第一和第二半导体材料的组合检测波长范围内的光。感测装置可以在第一和第二光敏二极管之间共享。

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