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1. 发明授权

US07045453B2 Very low effective dielectric constant interconnect structures and methods for fabricating the same 失效
标题翻译：非常低的有效介电常数互连结构及其制造方法
公开(公告)号：US07045453B2
公开(公告)日：2006-05-16
申请号：US11104764
申请日：2005-04-12
申请人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
发明人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76885 , H01L2924/0002 , H01L2924/00
摘要： A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less-robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.
摘要翻译：一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能的互连。布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中布置非常低的k和较不稳定的间隙填充电介质，使得该结构将耐用层与强度非常相似低k电介质用于互连电气性能。

2. 发明授权

US07023093B2 Very low effective dielectric constant interconnect Structures and methods for fabricating the same 有权
标题翻译：非常低的有效介电常数互连结构及其制造方法
公开(公告)号：US07023093B2
公开(公告)日：2006-04-04
申请号：US10280283
申请日：2002-10-24
申请人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
发明人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
IPC分类号： H01L23/48
CPC分类号： H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76885 , H01L2924/0002 , H01L2924/00
摘要： A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.
摘要翻译：一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能互连。布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中设置非常低的k和较不牢固的间隙填充电介质，使得该结构将耐用层与强度非常低 k电介质用于互连电性能。

3. 发明申请

US20070249156A1 METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY 审中-公开
标题翻译：用于实现超低K材料和生产的结构的硬掩模自由集成的方法
公开(公告)号：US20070249156A1
公开(公告)日：2007-10-25
申请号：US11672608
申请日：2007-02-08
申请人： Griselda Bonilla , Stephen M. Gates , Shom Ponoth , Satyanarayana V. Nitta , Sampath Purushothaman
发明人： Griselda Bonilla , Stephen M. Gates , Shom Ponoth , Satyanarayana V. Nitta , Sampath Purushothaman
IPC分类号： H01L21/4763
CPC分类号： H01L21/76826 , H01L21/02074 , H01L21/3105 , H01L21/31058 , H01L21/76883
摘要： A method is described for the repair of process induced damage sustained by low-k organosilicate dielectrics as a result of reactive ion etch, resist strip, wet clean and CMP operations in a hard mask free integration of these dielectrics into microelectronic interconnect structures incorporating a dielectric cap which is an etch stop and barrier layer. In situ reaction of the damaged regions with a suitable silylation agent just prior to a passivation barrier cap deposition is proposed as the most efficacious means to repair all the damage sustained by the dielectric. Variations of this method which include ex situ rather than in situ silylation are also described for use with hard mask free integration with selective barrier caps.
摘要翻译：描述了一种用于修复由低k有机硅酸盐电介质持续的过程诱导的损伤作为反应离子蚀刻，抗蚀剂条，湿清洁和CMP操作在将这些电介质纳入包含电介质的微电子互连结构的硬掩模中的CMP操作的方法盖是蚀刻停止层和阻挡层。在钝化阻挡层沉积之前，损伤区域与合适的甲硅烷基化剂的原位反应被提出作为修复由电介质所承受的所有损伤的最有效手段。还描述了包括异位原位甲硅烷基化的这种方法的变化，用于与选择性屏障帽的硬掩模自由积分。

4. 发明申请

US20080265415A1 Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same 有权
公开(公告)号：US20080265415A1
公开(公告)日：2008-10-30
申请号：US12164599
申请日：2008-06-30
申请人： Matthew E. Colburn , Stephen M. Gates , Jeffrey C. Hedrick , Elbert Huang , Satyanarayana V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
发明人： Matthew E. Colburn , Stephen M. Gates , Jeffrey C. Hedrick , Elbert Huang , Satyanarayana V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
IPC分类号： H01L23/52
CPC分类号： H05K3/0079 , H01L21/0331 , H01L21/76849 , H05K3/282 , H05K2203/1173 , Y10T428/24802
摘要： A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.

5. 发明申请

US20090311859A1 METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY 审中-公开
标题翻译：用于实现超低K材料和生产的结构的硬掩模自由集成的方法
公开(公告)号：US20090311859A1
公开(公告)日：2009-12-17
申请号：US12544088
申请日：2009-08-19
申请人： Griselda Bonilla , Stephen M. Gates , Shom Ponoth , Satyanarayana V. Nitta , Sampath Purushothaman
发明人： Griselda Bonilla , Stephen M. Gates , Shom Ponoth , Satyanarayana V. Nitta , Sampath Purushothaman
IPC分类号： H01L21/3205 , H01L21/31
CPC分类号： H01L21/76826 , H01L21/02074 , H01L21/3105 , H01L21/31058 , H01L21/76883
摘要： A method of fabricating an interconnect structure on a substrate includes steps of: providing a dielectric with at least one etched opening; filling the at least one etched opening with at least one conductive material; planarizing the conductive material to provide a planarized structure; subjecting the planarized structure to a plasma preclean process; and exposing the planarized structure to a silylating repair agent which is a silane derivative; and forming a dielectric cap layer on the planarized structure.
摘要翻译：在衬底上制造互连结构的方法包括以下步骤：为电介质提供至少一个蚀刻开口; 用至少一种导电材料填充所述至少一个蚀刻开口; 平面化导电材料以提供平坦化结构; 对平坦化结构进行等离子体预清洗处理; 并将平坦化结构暴露于作为硅烷衍生物的甲硅烷基化修复剂; 以及在所述平坦化结构上形成电介质盖层。

6. 发明申请

US20080265382A1 Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same 有权
标题翻译：生产自对准面膜的非光刻方法，由相同的组成制成的文章
公开(公告)号：US20080265382A1
公开(公告)日：2008-10-30
申请号：US12164647
申请日：2008-06-30
申请人： Matthew E. Colburn , Stephen M. Gates , Jeffrey C. Hedrick , Elbert Huang , Satyanarayana V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
发明人： Matthew E. Colburn , Stephen M. Gates , Jeffrey C. Hedrick , Elbert Huang , Satyanarayana V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
IPC分类号： H01L23/58 , C08L53/00
CPC分类号： H05K3/0079 , H01L21/0331 , H01L21/76849 , H05K3/282 , H05K2203/1173 , Y10T428/24802
摘要： A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.
摘要翻译：一种用于在衬底上的现有图案上形成自对准图案的方法，包括在载体中涂覆含有掩蔽材料的溶液的涂层，所述掩模材料对现有图案的部分具有亲和力; 并且允许掩模材料的至少一部分优先组装到现有图案的部分。该图案可以由具有第一原子组成的衬底的第一组区域和第二组衬底的区域组成，其具有不同于第一组成的第二原子组成。第一组区域可以包括一个或多个金属元件，并且第二组区域可以包括电介质。可以将第一和第二区域处理成具有不同的表面性质。按照该方法制造的结构。用于练习该方法的组合物。

7. 发明授权

US07439174B2 Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics 失效
标题翻译：多层硬掩模方案，用于SiCOH电介质的无损双重镶嵌加工
公开(公告)号：US07439174B2
公开(公告)日：2008-10-21
申请号：US11873936
申请日：2007-10-17
申请人： Timothy J. Dalton , Nicholas C. M. Fuller , Stephen M. Gates
发明人： Timothy J. Dalton , Nicholas C. M. Fuller , Stephen M. Gates
IPC分类号： H01L21/00
CPC分类号： H01L21/0331 , H01L21/76811 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/12576 , Y10T428/12611 , Y10T428/31667 , H01L2924/00
摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.
摘要翻译：具有用于90nm以上的有机硅酸盐玻璃基材料的互连结构，其中描述了使用线路优先方法的多层硬掩模的BEOL技术。本发明的互连结构实现了相应的改进的器件/互连性能，并且由于不暴露OSG材料以抵抗去除等离子体以及由于交替的无机/有机多层硬掩模堆叠而提供了实质的双镶嵌工艺窗口。后一特征意味着对于在特定蚀刻步骤期间被蚀刻的每个无机层，该领域中相应的图案转移层是有机的，反之亦然。

8. 发明授权

US06734096B2 Fine-pitch device lithography using a sacrificial hardmask 失效
标题翻译：使用牺牲硬掩模的精细间距器件光刻
公开(公告)号：US06734096B2
公开(公告)日：2004-05-11
申请号：US10053288
申请日：2002-01-17
申请人： Timothy J. Dalton , Minakshisundaran B. Anand , Michael D. Armacost , Shyng-Tsong Chen , Stephen M. Gates , Stephen E. Greco , Simon M. Karecki , Satyanarayana V. Nitta
发明人： Timothy J. Dalton , Minakshisundaran B. Anand , Michael D. Armacost , Shyng-Tsong Chen , Stephen M. Gates , Stephen E. Greco , Simon M. Karecki , Satyanarayana V. Nitta
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/76811 , H01L21/76826
摘要： A method is described for forming a metal pattern in a low-dielectric constant substrate. A hardmask is prepared which includes a low-k lower hardmask layer and a top hardmask layer. The top hardmask layer is a sacrificial layer with a thickness of about 200 Å, preferably formed of a refractory nitride, and which serves as a stopping layer in a subsequent CMP metal removal process. The patterning is performed using resist layers. Oxidation damage to the lower hardmask layer is avoided by forming a protective layer in the hardmask, or by using a non-oxidizing resist strip process.
摘要翻译：描述了在低介电常数衬底中形成金属图案的方法。准备了一个硬掩模，其包括低k较低的硬掩模层和顶部硬掩模层。顶部硬掩模层是厚度为约200埃的牺牲层，优选由耐火氮化物形成，并且在随后的CMP金属去除工艺中用作停止层。使用抗蚀剂层进行图案化。通过在硬掩模中形成保护层，或者通过使用非氧化抗蚀剂剥离工艺来避免对下部硬掩模层的氧化损伤。

9. 发明授权

US06617690B1 Interconnect structures containing stress adjustment cap layer 有权
标题翻译：互连结构包含应力调整盖层
公开(公告)号：US06617690B1
公开(公告)日：2003-09-09
申请号：US10218292
申请日：2002-08-14
申请人： Stephen M. Gates , Timothy J. Dalton , John A. Fitzsimmons
发明人： Stephen M. Gates , Timothy J. Dalton , John A. Fitzsimmons
IPC分类号： H01L2940
CPC分类号： H01L23/53295 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.
摘要翻译：本文提供了具有用于半导体器件的相对低的内应力和介电常数的新型互连结构。新颖的互连结构包括具有大于约20ppm的热膨胀系数的第一层和与其相关联的第一内部应力，第一层具有形成在其中的第一组金属线; 具有小于约20ppm的热膨胀系数的第二层和与其相关联的第二内应力，所述第二层在其中形成有第二组金属线; 以及形成在所述第一层和所述第二层之间的一个或多个应力调整盖层，所述盖层具有第三内应力以抵消所述第一层的第一应力和所述第二层的所述第二应力，并诱导有利的减轻互连结构上的应力。还提供了制造具有显着降低的内部应力的半导体器件的方法。

10. 发明授权

US08624323B2 BEOL structures incorporating active devices and mechanical strength 有权
标题翻译：包含有源器件和机械强度的BEOL结构
公开(公告)号：US08624323B2
公开(公告)日：2014-01-07
申请号：US13149797
申请日：2011-05-31
申请人： Stephen M. Gates , Daniel C. Edelstein , Satyanarayana V. Nitta
发明人： Stephen M. Gates , Daniel C. Edelstein , Satyanarayana V. Nitta
IPC分类号： H01L29/76 , H01L29/94 , H01L23/34 , H01L23/48 , H01L29/40
CPC分类号： H01L23/481 , H01L21/02667 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L23/5228 , H01L23/53238 , H01L24/80 , H01L25/18 , H01L25/50 , H01L27/016 , H01L27/0688 , H01L29/66984 , H01L29/861 , H01L29/872 , H01L2924/12032 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/00
摘要： A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate. A method of fabricating a monolithic integrated circuit using a single substrate, includes fabricating semiconductor devices on a substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.
摘要翻译：单片集成电路和方法包括基板，单片集成在基板上的多个半导体器件层以及具有互连多个半导体器件层的通孔的金属布线层。半导体器件层没有与衬底接合或结合界面。使用单个衬底制造单片集成电路的方法包括在衬底上制造半导体器件，在半导体器件上制造至少一个金属布线层，形成与至少一个金属布线层一体接触的至少一个电介质层形成通过所述至少一个电介质层的接触开口以暴露所述至少一个金属布线层的区域，从所述基板一体地形成所述电介质层上的第二半导体层，并与所述至少一个金属布线层通过所述接触开口，以及在所述第二半导体层中形成多个非线性半导体器件。

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