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1. 发明授权

US06475072B1 Method of wafer smoothing for bonding using chemo-mechanical polishing (CMP) 失效
标题翻译：使用化学机械抛光（CMP）的晶片平滑化方法
公开(公告)号：US06475072B1
公开(公告)日：2002-11-05
申请号：US09675841
申请日：2000-09-29
申请人： Donald F. Canaperi , Jack Oon Chu , Guy M. Cohen , Lijuan Huang , John Albrecht Ott , Michael F. Lofaro
发明人： Donald F. Canaperi , Jack Oon Chu , Guy M. Cohen , Lijuan Huang , John Albrecht Ott , Michael F. Lofaro
IPC分类号： B24B100
CPC分类号： H01L21/02074 , B24B37/345 , B24B49/006 , H01L21/02052 , H01L21/02065 , H01L21/31053 , H01L21/76251
摘要： A method and apparatus is described incorporating a semiconductor substrate, a CMP tool, a brush cleaning tool, and a chemical wafer cleaning tool. The CMP is performed with a down force of 1 psi, a backside air pressure of 0.5 psi, a platen speed of 50 rpm, a crarrier speed of 30 rpm and a slurry flow rate of 140 milliliters per minute.
摘要翻译：描述了结合半导体衬底，CMP工具，刷子清洁工具和化学晶片清洁工具的方法和装置。 CMP的下压力为1psi，背面空气压力为0.5psi，压板速度为50rpm，碎屑速度为30rpm，淤浆流速为140毫升/分钟。

2. 发明授权

US06524935B1 Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique 有权
标题翻译：通过氢诱导层转移技术制备绝缘体上的应变Si / SiGe
公开(公告)号：US06524935B1
公开(公告)日：2003-02-25
申请号：US09675840
申请日：2000-09-29
申请人： Donald F. Canaperi , Jack Oon Chu , Christopher P. D'Emic , Lijuan Huang , John Albrecht Ott , Hon-Sum Philip Wong
发明人： Donald F. Canaperi , Jack Oon Chu , Christopher P. D'Emic , Lijuan Huang , John Albrecht Ott , Hon-Sum Philip Wong
IPC分类号： H01L2136
CPC分类号： H01L21/76254
摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) is described incorporating growing epitaxial Si1−yGey layers on a semiconductor substrate, implanting hydrogen into a selected Si1−yGey layer to form a hydrogen-rich defective layer, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and separating two substrates at the hydrogen-rich defective layer. The separated substrates may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1−yGey, and strained Si1−yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1−yGeyC.
摘要翻译：描述了在半导体衬底上生长的外延Si1-yGey层上生长在绝缘体上的弛豫SiGe（SGOI）上形成应变Si或SiGe的方法，将氢注入到选定的Si1-yGey层中以形成富氢缺陷层，通过化学机械抛光，通过热处理将两个基板结合在一起，并在富氢缺陷层处分离两个基板。分离的衬底可以通过CMP平滑CMP的上表面，用于外延沉积弛豫Si1-yGey，并且应变Si1-yGey取决于组成，应变Si，应变SiC，应变Ge，应变GeC和应变Si1-yGeyC。

3. 发明申请

US20090267052A1 LAYER TRANSFER OF LOW DEFECT SiGe USING AN ETCH-BACK PROCESS 失效
公开(公告)号：US20090267052A1
公开(公告)日：2009-10-29
申请号：US12181613
申请日：2008-07-29
申请人： Jack Oon Chu , David R. DiMilia , Lijuan Huang
发明人： Jack Oon Chu , David R. DiMilia , Lijuan Huang
IPC分类号： H01L29/12
CPC分类号： H01L21/76256 , H01L21/2007
摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.

4. 发明申请

US20090026495A1 LAYER TRANSFER OF LOW DEFECT SiGe USING AN ETCH-BACK PROCESS 审中-公开
标题翻译：使用回流过程的低缺陷SiGe的层传输
公开(公告)号：US20090026495A1
公开(公告)日：2009-01-29
申请号：US12181489
申请日：2008-07-29
申请人： Jack Oon Chu , David R. DiMilia , Lijuan Huang
发明人： Jack Oon Chu , David R. DiMilia , Lijuan Huang
IPC分类号： H01L29/161
CPC分类号： H01L21/76256 , H01L21/2007
摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.
摘要翻译：描述了在半导体衬底上增长的外延Si1-yGey层，通过Chemo-Mechanical Polishing平滑表面，通过热粘合将两个衬底粘合在一起，在绝缘体上松弛的SiGe（SiO）或Si异质结构上的SiGe上形成应变Si或SiGe的方法处理并通过使用SiGe本身作为蚀刻停止的高选择性蚀刻将SiGe层从一个衬底转移到另一衬底。转移的SiGe层可以通过CMP平滑CMP，用于外延沉积弛豫Si1-yGey，并且应变Si1-yGey取决于组成，应变Si，应变SiC，应变Ge，应变GeC和应变Si1-yGeyC或重度掺杂层以形成SiGe / Si异质结二极管的电接触。

5. 发明授权

US07427773B2 Layer transfer of low defect SiGe using an etch-back process 有权
标题翻译：使用回蚀工艺对低缺陷SiGe进行层传输
公开(公告)号：US07427773B2
公开(公告)日：2008-09-23
申请号：US10948421
申请日：2004-09-23
申请人： Jack Oon Chu , David R. DiMilia , Lijuan Huang
发明人： Jack Oon Chu , David R. DiMilia , Lijuan Huang
IPC分类号： H01L29/737
CPC分类号： H01L21/76256 , H01L21/2007
摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1−yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly selective etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1−yGey, and strained Si1−yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1−yGeyC or a heavily doped layer to make electrical contacts for the SiGe/Si heterojunction diodes.
摘要翻译：描述了在松散的SiGe绝缘体上（SGOI）上形成应变Si或SiGe的方法或Si异质结构上的SiGe的方法，该方法包括生长外延Si 1-y Ge层半导体衬底，通过化学机械抛光的平滑表面，通过热处理将两个衬底结合在一起，并且通过使用SiGe本身作为蚀刻停止层的高选择性蚀刻将SiGe层从一个衬底转移到另一衬底。转移的SiGe层可以通过CMP平滑其上表面，用于外延沉积弛豫的Si 1-y Ge y Si，并且应变Si 1-y

6. 发明授权

US06890835B1 Layer transfer of low defect SiGe using an etch-back process 失效
标题翻译：使用回蚀工艺对低缺陷SiGe进行层传输
公开(公告)号：US06890835B1
公开(公告)日：2005-05-10
申请号：US09692606
申请日：2000-10-19
申请人： Jack Oon Chu , David R. DiMilia , Lijuan Huang
发明人： Jack Oon Chu , David R. DiMilia , Lijuan Huang
IPC分类号： H01L21/331 , H01L21/02 , H01L21/20 , H01L21/336 , H01L21/338 , H01L21/762 , H01L27/12 , H01L29/161 , H01L29/737 , H01L29/778 , H01L29/786 , H01L29/812 , H01L29/861 , H01L31/10 , H01L21/30 , C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14 , C30B29/10 , H01L21/46
CPC分类号： H01L21/76256 , H01L21/2007
摘要： A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) or a SiGe on Si heterostructure is described incorporating growing epitaxial Si1-yGey layers on a semiconductor substrate, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and transferring the SiGe layer from one substrate to the other via highly seletive etching using SiGe itself as the etch-stop. The transferred SiGe layer may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1-yGey, and strained Si1-yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1-yGeyC or a heavily doped layer to make electrical contacts of the SiGe/Si heterojunction diodes.
摘要翻译：描述了在松散的SiGe绝缘体上（SGOI）上形成应变Si或SiGe的方法或Si异质结构上的SiGe的方法，该方法包括生长外延Si 1-y Ge层半导体衬底，通过化学机械抛光的平滑表面，通过热处理将两个衬底粘合在一起，并通过使用SiGe本身作为蚀刻停止层的高精密蚀刻将SiGe层从一个衬底转移到另一衬底。转移的SiGe层可以通过CMP平滑其上表面，用于外延沉积弛豫的Si 1-y Ge y Si，并且应变Si 1-y

7. 发明授权

US06797604B2 Method for manufacturing device substrate with metal back-gate and structure formed thereby 有权
标题翻译：制造具有金属背栅的器件衬底和由此形成的结构的方法
公开(公告)号：US06797604B2
公开(公告)日：2004-09-28
申请号：US09817120
申请日：2001-03-27
申请人： Kevin K. Chan , Lijuan Huang , Fenton R. McFeely , Paul M. Solomon , Hon-Sum Philip Wong
发明人： Kevin K. Chan , Lijuan Huang , Fenton R. McFeely , Paul M. Solomon , Hon-Sum Philip Wong
IPC分类号： H01L214763
CPC分类号： H01L29/66772 , H01L21/76251 , H01L29/78648
摘要： A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.
摘要翻译：形成半导体器件的方法（和结果）包括在衬底和金属背栅上形成金属反向栅极，在金属背栅上形成钝化层，以防止金属背栅极反应具有自由基物质，并且在基材和金属背栅之间提供中间胶合层以增强粘合性。

8. 发明授权

US09475206B2 Craft punch with replaceable cutting tool 有权
标题翻译：工艺冲孔用可更换刀具
公开(公告)号：US09475206B2
公开(公告)日：2016-10-25
申请号：US14364678
申请日：2011-12-16
申请人： Lijuan Huang
发明人： Lijuan Huang
IPC分类号： B26F1/14 , B26F1/02 , B26F1/36 , B26D7/26 , B26F1/32
CPC分类号： B26F1/14 , B26D2007/2607 , B26F1/02 , B26F1/32 , B26F1/36
摘要： A craft punch with a replaceable cutting tool includes a main body having an upper part and a lower part which are spaced up and down. The upper part has a passage, and the lower part has a receiving part to movably receive a lower cutting mold holder. An upper cutting mold holder receiving component could be installed in the passage movably up and down, the upper side of the receiving component bulges to form a tubular part, and one side of the receiving component back to the tubular part is provided with a receiving part which could movably receive an upper cutting mold; a cover plate covers the upper end of the passage and is provided with a through hole allowing the tubular part to pass through an upper bulge, and an upper cover covers the upper side of the cover plate, and is connected with the tubular part.
摘要翻译：具有可替换切割工具的工艺冲头包括具有上下部分的上部和下部的主体。上部具有通道，下部具有可移动地容纳下切割模夹持器的接纳部。上切割模保持器接收部件可以可上下移动地安装在通道中，接收部件的上侧凸出形成管状部分，并且接收部件的一侧返回到管状部分设置有接收部分其可移动地容纳上切割模具; 盖板覆盖通道的上端，并且设置有允许管状部件穿过上凸起的通孔，并且上盖覆盖盖板的上侧，并且与管状部件连接。

9. 发明授权

US07145212B2 Method for manufacturing device substrate with metal back-gate and structure formed thereby 有权
公开(公告)号：US07145212B2
公开(公告)日：2006-12-05
申请号：US10868791
申请日：2004-06-17
申请人： Kevin K. Chan , Lijuan Huang , Fenton R. McFeely , Paul M. Solomon , Hon-Sum Philip Wong
发明人： Kevin K. Chan , Lijuan Huang , Fenton R. McFeely , Paul M. Solomon , Hon-Sum Philip Wong
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L21/76251 , H01L29/78648
摘要： A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.

10. 外观设计

USD1011444S1 Elephant toy 有权
公开(公告)号：USD1011444S1
公开(公告)日：2024-01-16
申请号：US29893615
申请日：2023-05-31
申请人： Lijuan Huang
设计人： Lijuan Huang
摘要： FIG. 1 is a perspective view of an elephant toy showing our new design;
FIG. 2 is another perspective view thereof;
FIG. 3 is a front elevational view thereof;
FIG. 4 is a rear elevational view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right sideview thereof;
FIG. 7 is a top plan view thereof;
FIG. 8 is a rear elevational view thereof; and,
FIG. 9 is a partial enlarged view taken from FIG. 1 thereof.
The broken lines depict portions of the elephant toy that form no part of the claimed design.
The dot-dash broken lines indicating an enlargement portion of the design form no part of the claimed design.

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