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1. 发明授权

US08648653B2 Method and apparatus for reducing interference 有权
标题翻译：减少干扰的方法和装置
公开(公告)号：US08648653B2
公开(公告)日：2014-02-11
申请号：US12650546
申请日：2009-12-31
申请人： David R. Welland , Donald A. Kerth , Caiyi Wang
发明人： David R. Welland , Donald A. Kerth , Caiyi Wang
IPC分类号： H03K5/00
CPC分类号： H05K9/00 , H03L7/18 , H05K1/0216 , H05K3/10 , Y10T29/49124
摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.
摘要翻译：提供一种减少电路干扰的方法和装置。提供管理策略，以减少参考杂散和电路干扰。管理策略使用一种或多种减少数字电流，最小化互感，利用场消除，防止泄漏电流和/或管理阻抗的技术的组合。这些技术可以单独使用，或者优选地彼此组合使用。

2. 发明授权

US08421529B2 Method and apparatus for reducing interference 有权
公开(公告)号：US08421529B2
公开(公告)日：2013-04-16
申请号：US12650543
申请日：2009-12-31
申请人： David R. Welland , Donald A. Kerth , Caiyi Wang
发明人： David R. Welland , Donald A. Kerth , Caiyi Wang
IPC分类号： H03K5/00
CPC分类号： H05K9/00 , H03L7/18 , H05K1/0216 , H05K3/10 , Y10T29/49124
摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

3. 发明授权

US07941102B2 Partitioned radio-frequency apparatus and associated methods 有权
标题翻译：分频射频设备及相关方法
公开(公告)号：US07941102B2
公开(公告)日：2011-05-10
申请号：US11931656
申请日：2007-10-31
申请人： Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu Shankar Srinivasan
发明人： Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu Shankar Srinivasan
IPC分类号： H04B1/40
CPC分类号： H04B1/109 , H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064 , H04L27/2649
摘要： Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.
摘要翻译：射频（RF）设备包括接收模拟电路，其接收RF信号并且向与接收机模拟电路协作起作用的接收机数字电路提供至少一个数字信号。接收机模拟电路和接收机数字电路被分割，使得接收机模拟电路和接收机数字电路之间的干扰效应趋于降低。

4. 发明申请

US20100167684A1 QUADRATURE SIGNAL GENERATION IN RADIO-FREQUENCY APPARATUS AND ASSOCIATED METHODS 有权
标题翻译：无线电频率装置和相关方法的平均信号产生
公开(公告)号：US20100167684A1
公开(公告)日：2010-07-01
申请号：US12579591
申请日：2009-10-15
申请人： Donald A. Kerth
发明人： Donald A. Kerth
IPC分类号： H04B1/16
CPC分类号： H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency (RF) apparatus, which may reside in a receiver or transceiver, includes receive-path circuitry. The receive-path circuitry includes a poly-phase filter and a harmonic filter. The poly-phase filter accepts an input signal and generates two output signals. One output signal of the poly-phase filter constitutes an in-phase (I) signal. The other output signal of the poly-phase filter constitutes a quadrature (Q) signal. The a harmonic filter couples to the poly-phase filter. The harmonic filter accepts as input signals the in-phase and quadrature output signals of the poly-phase filter.
摘要翻译：可以驻留在接收机或收发机中的射频（RF）设备包括接收路径电路。接收路径电路包括多相滤波器和谐波滤波器。多相滤波器接受输入信号并产生两个输出信号。多相滤波器的一个输出信号构成同相（I）信号。多相滤波器的另一输出信号构成正交（Q）信号。谐波滤波器耦合到多相滤波器。谐波滤波器接收多相滤波器的同相和正交输出信号作为输入信号。

5. 发明授权

US07676210B2 Method for performing dual mode image rejection calibration in a receiver 有权
标题翻译：在接收机中执行双模式镜像抑制校准的方法
公开(公告)号：US07676210B2
公开(公告)日：2010-03-09
申请号：US11227797
申请日：2005-09-15
申请人： Tod Paulus , Donald A. Kerth , Srihari Adireddy , G. Diwakar Vishakhadatta
发明人： Tod Paulus , Donald A. Kerth , Srihari Adireddy , G. Diwakar Vishakhadatta
IPC分类号： H04B1/10
CPC分类号： H04B1/30 , H04B17/21
摘要： A method is disclosed for performing dual mode image rejection calibration in a receiver. A first image correction factor is acquired for use in a receiver system using a first known signal associated with a first signal band during a startup mode. The first image correction factor is adjusted incrementally during a normal operation mode. A radio frequency (RF) signal associated with the first signal band is received using the first image correction factor during the normal operation mode.
摘要翻译：公开了一种用于在接收机中执行双模式拒绝校准的方法。在启动模式期间，使用与第一信号频带相关联的第一已知信号在接收机系统中获取第一图像校正因子。在正常操作模式期间，第一图像校正因子被递增地调整。在正常操作模式期间使用第一图像校正因子接收与第一信号频带相关联的射频（RF）信号。

6. 发明申请

US20080002786A1 WIRELESS COMMUNICATION DEVICE WITH SELF CALIBRATION FEATURE FOR CONTROLLING POWER OUTPUT 有权
标题翻译：具有自校准功能的无线通信设备，用于控制电源输出
公开(公告)号：US20080002786A1
公开(公告)日：2008-01-03
申请号：US11427800
申请日：2006-06-30
申请人： Donald A. Kerth , Srinath Sridharan
发明人： Donald A. Kerth , Srinath Sridharan
IPC分类号： H04L25/49
CPC分类号： H04W52/52 , H04B17/13 , H04W52/04
摘要： A wireless communication device is disclosed which employs a minimal number of power calibrations to set the output power of the device to a specified output power level. In one embodiment, the disclosed communication device includes a self calibrating feature that sets the output power level during initialization of the device.
摘要翻译：公开了一种无线通信设备，其采用最小数量的功率校准来将设备的输出功率设置为指定的输出功率电平。在一个实施例中，所公开的通信设备包括在设备的初始化期间设置输出功率电平的自校准特征。

7. 发明授权

US07292091B1 Method and apparatus for reducing interference 有权
公开(公告)号：US07292091B1
公开(公告)日：2007-11-06
申请号：US11170380
申请日：2005-06-29
申请人： David R. Welland , Donald A. Kerth , Caiyi Wang
发明人： David R. Welland , Donald A. Kerth , Caiyi Wang
IPC分类号： H03K5/00
CPC分类号： H05K9/00 , H03L7/18 , H05K1/0216 , H05K3/10 , Y10T29/49124
摘要： A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

8. 发明授权

US06650264B1 Quadrature sampling architecture and method for analog-to-digital converters 有权
标题翻译：模数转换器的正交采样架构和方法
公开(公告)号：US06650264B1
公开(公告)日：2003-11-18
申请号：US09414209
申请日：1999-10-07
申请人： Brian P. Lum Shue Chan , Brian D. Green , Donald A. Kerth
发明人： Brian P. Lum Shue Chan , Brian D. Green , Donald A. Kerth
IPC分类号： H03M300
CPC分类号： H03M1/1215 , H03M3/40 , H03M3/47
摘要： Quadrature sampling architecture and method are disclosed for analog-to-digital converters that provide improved digital output signals over prior quadrature mixing implementations. Sampling circuitry according to the present invention samples an input signal with a first and second sampling signals to produce real and imaginary sampled output signals. The first sampling signal, which is associated with the real sampled output signal, is delayed by one-fourth cycle with respect to the second sampling signal, which is associated with the imaginary sampled output signal. This one-fourth cycle sampling signal difference allows for simplified construction of the sampling circuitry. In addition, filter circuitry according to the present invention processes the real and imaginary digital data output signals so that the imaginary digital data output signal is advanced by one-fourth cycle with respect to the real digital data output signal. This one-fourth cycle relative advance tends to eliminate undesirable magnitude distortion and error signals in complex digital output signals that have been mixed down to baseband. Furthermore, the real and imaginary signal paths may be interchanged and still take advantage of the present invention.
摘要翻译：公开了用于模数转换器的正交采样架构和方法，其在现有的正交混频实现方面提供改进的数字输出信号。根据本发明的采样电路用第一和第二采样信号对输入信号进行采样以产生实数和虚数采样的输出信号。与实际采样输出信号相关联的第一采样信号相对于与虚拟采样输出信号相关联的第二采样信号被延迟四分之一周期。这个四分之一周期采样信号差异允许采样电路的简化结构。此外，根据本发明的滤波器电路处理实数和虚数数字输出信号，使得虚数数字数据输出信号相对于实数数字数据输出信号提前四分之一。这个四分之一周期的相对提前趋向于消除已经被混合到基带的复杂数字输出信号中的不期望的幅度失真和误差信号。此外，实信号路径和虚信号路径可以互换，并且仍然利用本发明。

9. 发明授权

US06311050B1 Single integrated circuit phase locked loop for synthesizing high-frequency signals for wireless communications and method for operating same 失效
标题翻译：用于合成用于无线通信的高频信号的单集成电路锁相环及其操作方法
公开(公告)号：US06311050B1
公开(公告)日：2001-10-30
申请号：US09087174
申请日：1998-05-29
申请人： David R. Welland , Caiyi Wang , Donald A. Kerth
发明人： David R. Welland , Caiyi Wang , Donald A. Kerth
IPC分类号： H04Q720
CPC分类号： H03L7/10 , H03J2200/10 , H03L7/099 , H03L7/199 , H03L7/23
摘要： A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. The invention disclosed avoids the need for a traditional varactor implementation in the VCO, for a traditional large capacitor component in the loop filter, and for component trimming during processing and thereby provides a high-frequency frequency synthesizer that may be fully integrated on a single chip except for an external inductor.
摘要翻译：公开了一种用于合成高频信号的方法和装置，其克服了与现有实施相关的集成问题，同时满足苛刻的相位噪声和其他杂质要求。在一个实施例中，公开了具有可变电容的压控振荡器（VCO）的锁相环（PLL）频率合成器，该可变电容包括连续可变电容的离散可变电容。离散可变电容可以提供可变电容的粗调谐调节，并且连续可变电容可以提供可变电容的精细调谐。所公开的发明避免了在VCO中对传统的变容二极管实现的需要，对于环路滤波器中的传统大电容器组件以及在处理期间的组件调整，从而提供可以完全集成在单个芯片上的高频频率合成器外部电感除外。

10. 发明授权

US5412348A Compound triple cascoded mirror 失效
标题翻译：复合三联共享镜
公开(公告)号：US5412348A
公开(公告)日：1995-05-02
申请号：US87842
申请日：1993-07-01
申请人： Dan B. Kasha , Donald A. Kerth
发明人： Dan B. Kasha , Donald A. Kerth
IPC分类号： H03F3/345 , H03F3/45 , H03F3/16
CPC分类号： H03F3/345 , H03F3/45188
摘要： A triple cascoded mirror active load includes three transistors (20), (26) and (28) in a first leg and three transistors (22), (30) and (34) in an output leg connected to an output node (18). The first leg receives a current on an input node (14) on the drain of transistor (20). Transistor (20) has the gate thereof connected to the drain of transistor (26) with the gates of transistors (24) and (30) connected together and to a bias voltage. Transistor (20) is mirrored to transistor (22) by connecting the gates thereof together. Similarly, the gates of transistors (28) and (34) are connected together and also to the node (14). In this manner, the node (14) receives a low impedance on the input thereto, whereas the gate of transistor (22) sees a high impedance thereto and with only two transistors, transistors 26 and 28, disposed in a loop as a ratioed cascoded configuration.
摘要翻译：三重级联反射镜有源负载包括第一支路中的三个晶体管（20），（26）和（28）以及连接到输出节点（18）的输出支路中的三个晶体管（22），（30）和（34）。第一支路在晶体管（20）的漏极上的输入节点（14）上接收电流。晶体管（20）的栅极连接到晶体管（26）的漏极，晶体管（24）和（30）的栅极连接在一起并且具有偏置电压。晶体管（20）通过将其栅极连接在一起而被镜像到晶体管（22）。类似地，晶体管（28）和（34）的栅极连接在一起，并且连接到节点（14）。以这种方式，节点（14）在其输入端接收低阻抗，而晶体管（22）的栅极看到高阻抗，并且只有两个晶体管晶体管26和28设置在环路中，作为比例级联组态。

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