专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060283638A1 Shirttails for reducing damaging effects of cuttings 有权
公开(公告)号：US20060283638A1
公开(公告)日：2006-12-21
申请号：US11511119
申请日：2006-08-28
申请人： Christopher Beuershausen , Raul Lema , Ronald Hales , Don Nguyen , Gregory Ricks , Chih Lin , Terry Koltermann , Mark Morris , Chris McCarty , Ronald Jones , James Overstreet , Rudolf Pessier
发明人： Christopher Beuershausen , Raul Lema , Ronald Hales , Don Nguyen , Gregory Ricks , Chih Lin , Terry Koltermann , Mark Morris , Chris McCarty , Ronald Jones , James Overstreet , Rudolf Pessier
IPC分类号： E21B10/08
CPC分类号： E21B10/08
摘要： An earth-boring bit has a bit body that includes head sections, each having depending bit legs with a circumferentially extending outer surface, a leading side, and a trailing side. A bearing shaft depends inwardly from each of the bit legs for mounting a cutter. The bit includes a beveled surface formed at a junction of the leading side and the outer surface of each bit leg. The beveled surface is angled relative to a radial plane emenating from the axis of the bit. The angle of the beveled surface is at least 20 degrees, and extends to an inner surface of the bit leg. The bit can also have a layer of hardfacing on the leading, trailing and shirttail surfaces of the bit leg. A diversion finger of hardfacing extends circumferentially to direct cuttings.

2. 发明申请

US20060021800A1 Shirttails for reducing damaging effects of cuttings 有权
标题翻译：用于减少切屑的破坏性影响的衬衫
公开(公告)号：US20060021800A1
公开(公告)日：2006-02-02
申请号：US10902222
申请日：2004-07-29
申请人： Christopher Beuershausen , Raul Lema , Ronald Hales , Don Nguyen , Gregory Ricks , Chih Lin , Terry Koltermann , Mark Morris , Chris McCarty , Ronald Jones , James Overstreet , Rudolf Otto Pessier
发明人： Christopher Beuershausen , Raul Lema , Ronald Hales , Don Nguyen , Gregory Ricks , Chih Lin , Terry Koltermann , Mark Morris , Chris McCarty , Ronald Jones , James Overstreet , Rudolf Otto Pessier
IPC分类号： E21B10/00 , E21B10/36
CPC分类号： E21B10/08
摘要： An earth-boring bit has a bit body that includes head sections, each having depending bit legs with a circumferentially extending outer surface, a leading side, and a trailing side. A bearing shaft depends inwardly from each of the bit legs for mounting a cutter. The bit includes a beveled surface formed at a junction of the leading side and the outer surface of each bit leg. The beveled surface is angled relative to a radial plane emenating from the axis of the bit. The angle of the beveled surface is at least 20 degrees, and extends to an inner surface of the bit leg. The bit can also have a layer of hardfacing on the leading, trailing and shirttail surfaces of the bit leg. A diversion finger of hardfacing extends circumferentially to direct cuttings.
摘要翻译：钻头具有包括头部部分的头部部件，每个头部部分具有具有周向延伸的外表面，前导侧和后侧的依附的位腿。轴承轴从每个钻头腿向内取向，用于安装切割器。该钻头包括形成在每个钻头腿的前侧和外表面的接合处的斜面。倾斜表面相对于从钻头的轴线发出的径向平面成角度。斜面的角度至少为20度，并且延伸到钻头的内表面。该位还可以在位腿的前导，尾部和衬衫表面上具有一层硬面。硬面的转向手指周向延伸以直接切割。

3. 发明申请

US20050211474A1 Gage surface scraper 失效
标题翻译：量规表面刮刀
公开(公告)号：US20050211474A1
公开(公告)日：2005-09-29
申请号：US10809644
申请日：2004-03-25
申请人： Don Nguyen , Terry Koltermann , Gregory Ricks , Mark Morris , Chris McCarty , Chih Lin
发明人： Don Nguyen , Terry Koltermann , Gregory Ricks , Mark Morris , Chris McCarty , Chih Lin
IPC分类号： E21B10/08
CPC分类号： E21B10/08
摘要： A gage scraper cleans mud from the gage surface of a rotary cone of a drill bit. The bit has a body having at least one leg depending therefrom, a bearing pin secured to each leg, and a rotary cutting cone mounted to the bearing pin. The cone has a conical gage surface. The gage scraper mounts on the inside of each leg and protrudes from the leg toward the cone into close proximity with the gage surface.
摘要翻译：量具刮刀从钻头的旋转锥体的量规表面清除泥浆。所述钻头具有至少一个从其悬挂的支脚的主体，固定到每个支腿的支承销以及安装在所述支承销上的旋转切割锥。锥体具有锥形表面。量规刮刀安装在每个腿的内侧，并从腿部朝向锥体突出，与计量表面紧密接近。

4. 发明申请

US20050042853A1 Active area bonding compatible high current structures 有权
标题翻译：有源区粘合兼容高电流结构
公开(公告)号：US20050042853A1
公开(公告)日：2005-02-24
申请号：US10698184
申请日：2003-10-31
申请人： John Gasner , Michael Church , Sameer Parab , Paul Bakeman , David Decrosta , Robert Lomenick , Chris McCarty
发明人： John Gasner , Michael Church , Sameer Parab , Paul Bakeman , David Decrosta , Robert Lomenick , Chris McCarty
IPC分类号： H01L23/485 , H01L21/44
CPC分类号： H01L24/05 , H01L23/528 , H01L23/53295 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05166 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/01007 , H01L2224/45099
摘要： An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.
摘要翻译：一个集成电路，具有一个接合焊盘下的电路。在一个实施例中，集成电路包括衬底，顶部导电层，一个或多个中间导电层，绝缘材料和器件层。顶部导电层具有至少一个焊盘和相对刚性材料的子层。一个或多个中间导电层形成在顶部导电层和衬底之间。绝缘材料层分离导电层。此外，绝缘材料层的一层相对较硬，并且位于顶部导电层和最靠近顶部导电层的中间导电层之间。器件形成在集成电路中。此外，至少最靠近顶部导电层的中间导电层适用于接合焊盘下的选择器件的功能互连。

5. 发明申请

US20070184645A1 ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES 有权
标题翻译：主动区域结合兼容的高电流结构
公开(公告)号：US20070184645A1
公开(公告)日：2007-08-09
申请号：US11737392
申请日：2007-04-19
申请人： John Gasner , Michael Church , Sameer Parab , Paul Bakeman Jr. , David Decrosta , Robert Lomenick , Chris McCarty
发明人： John Gasner , Michael Church , Sameer Parab , Paul Bakeman Jr. , David Decrosta , Robert Lomenick , Chris McCarty
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L24/05 , H01L23/528 , H01L23/53295 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05166 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/01007 , H01L2224/45099
摘要： A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad.
摘要翻译：提供一种形成半导体结构的方法。一种方法包括在衬底和接合衬垫之间形成器件区域。在接合焊盘和具有间隙的器件区域之间形成导体。使用比导体硬的绝缘材料填充间隙，以形成延伸穿过导体的相对硬的材料的支柱，并在导体和接合垫之间形成绝缘材料的绝缘层。

6. 发明授权

US06350640B1 CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor 失效
标题翻译： CMOS集成电路架构结合深注入发射极区域形成辅助双极晶体管
公开(公告)号：US06350640B1
公开(公告)日：2002-02-26
申请号：US08276290
申请日：1994-07-18
申请人： Robert T. Fuller , Chris McCarty , John T. Gasner , Michael D. Church
发明人： Robert T. Fuller , Chris McCarty , John T. Gasner , Michael D. Church
IPC分类号： H01L218238
CPC分类号： H01L27/0623
摘要： To program a CMOS memory, an auxiliary bipolar transistor is formed in a P-well adjacent to the P-well of an NMOS device of the CMOS memory, the auxiliary transistor being capable of forcing a large magnitude current through a fusible link, so as to program the electronic state of the CMOS memory cell into a prescribed binary (1/0) condition. A separate implant mask for the emitter region of the auxiliary transistor allows the geometry and impurity concentration profile of the emitter region to be tailored by a deep dual implant, so that the impurity concentration of the emitter region is not decreased, and yields a reduced base width for the auxiliary transistor to provide a relatively large current gain to blow the fuse, while allowing the doping parameters of the source/drain regions of the CMOS structure to be separately established to prevent thyristor latch-up.
摘要翻译：为了编程CMOS存储器，辅助双极晶体管形成在与CMOS存储器的NMOS器件的P阱相邻的P阱中，辅助晶体管能够通过可熔链路强制大幅度电流，因此将CMOS存储单元的电子状态编程为规定的二进制（1/0）条件。用于辅助晶体管的发射极区域的单独的注入掩模允许通过深度双注入来调整发射极区域的几何形状和杂质浓度分布，使得发射极区域的杂质浓度不降低，并且产生降低的基极宽度用于提供相对较大的电流增益来熔断熔丝，同时允许分别建立CMOS结构的源/漏区的掺杂参数以防止晶闸管闭锁。

7. 发明申请

US20060099823A1 Active area bonding compatible high current structures 有权
公开(公告)号：US20060099823A1
公开(公告)日：2006-05-11
申请号：US11305987
申请日：2005-12-19
申请人： John Gasner , Michael Church , Sameer Parab , Paul Bakeman , David Decrosta , Robert Lomenick , Chris McCarty
发明人： John Gasner , Michael Church , Sameer Parab , Paul Bakeman , David Decrosta , Robert Lomenick , Chris McCarty
IPC分类号： H01L21/31
CPC分类号： H01L24/05 , H01L23/528 , H01L23/53295 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05166 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/01007 , H01L2224/45099
摘要： An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.

8. 发明申请

US20070187837A1 ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES 审中-公开
标题翻译：主动区域结合兼容的高电流结构
公开(公告)号：US20070187837A1
公开(公告)日：2007-08-16
申请号：US11737395
申请日：2007-04-19
申请人： John Gasner , Michael Church , Sameer Parab , Paul Bakeman , David Decrosta , Robert Lomenick , Chris McCarty
发明人： John Gasner , Michael Church , Sameer Parab , Paul Bakeman , David Decrosta , Robert Lomenick , Chris McCarty
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/05 , H01L23/528 , H01L23/53295 , H01L24/03 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05166 , H01L2224/05624 , H01L2224/05647 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/01007 , H01L2224/45099
摘要： A semiconductor structure is provided. In one embodiment, the structure comprises at least one active device located in a substrate and directly under a bond pad. A conductor is located between the bond pad and the substrate. The conductor has a plurality of gaps filled with insulating material. The insulating material is harder than the conductor.
摘要翻译：提供半导体结构。在一个实施例中，该结构包括至少一个位于衬底中并且直接在接合焊盘下的有源器件。导体位于接合焊盘和基板之间。导体具有填充有绝缘材料的多个间隙。绝缘材料比导体硬。

9. 发明授权

US4553315A N Contact compensation technique 失效
标题翻译： N接触补偿技术
公开(公告)号：US4553315A
公开(公告)日：1985-11-19
申请号：US597060
申请日：1984-04-05
申请人： Chris McCarty
发明人： Chris McCarty
IPC分类号： H01L21/265 , H01L21/285 , H01L21/768 , H01L29/08 , H01L21/28
CPC分类号： H01L29/0847 , H01L21/26513 , H01L21/28525 , H01L21/76885 , Y10S148/083
摘要： The contact for N channel devices in a CMOS process is formed by ion implanting N-type impurities through contact apertures in the dielectric layer to a depth less than the source and drain regions and a layer of conductive material is applied without intermediate etching and delineated.
摘要翻译： CMOS工艺中的N沟道器件的接触是通过将介电层中的接触孔离子注入N型杂质形成的深度小于源极和漏极区域的深度，并且在没有中间蚀刻和描绘的情况下施加一层导电材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式