专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09000808B2 Input pin state detection circuit and method therefor 有权
标题翻译：输入引脚状态检测电路及其方法
公开(公告)号：US09000808B2
公开(公告)日：2015-04-07
申请号：US12790362
申请日：2010-05-28
申请人： Dominicus M. Roozeboom , Sharad Murari , Harold Garth Hanson
发明人： Dominicus M. Roozeboom , Sharad Murari , Harold Garth Hanson
IPC分类号： H03K5/153 , H03K19/173 , H03M1/36
CPC分类号： H03K19/017581 , H03K5/24 , H03K19/173 , H03M1/365
摘要： A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.
摘要翻译：状态检测电路有助于检测输入引脚相对于多种不同类型的输入电路的状态。根据示例实施例，状态检测电路包括多个比较器和电路部件，其被配置为提供多个二进制输出信号，其共同指示比较器耦合到的输入引脚的状态。状态检测电路被配置为便于基于二进制输出信号检测几种不同类型的输入电路。

2. 发明申请

US20110291704A1 Input Pin State Detection Circuit and Method Therefor 有权
标题翻译：输入引脚状态检测电路及其方法
公开(公告)号：US20110291704A1
公开(公告)日：2011-12-01
申请号：US12790362
申请日：2010-05-28
申请人： Dominicus M. Roozeboom , Sharad Murari , Harold Garth Hanson
发明人： Dominicus M. Roozeboom , Sharad Murari , Harold Garth Hanson
IPC分类号： H03K5/22
CPC分类号： H03K19/017581 , H03K5/24 , H03K19/173 , H03M1/365
摘要： A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.
摘要翻译：状态检测电路有助于检测输入引脚相对于多种不同类型的输入电路的状态。根据示例实施例，状态检测电路包括多个比较器和电路部件，其被配置为提供多个二进制输出信号，其共同指示比较器耦合到的输入引脚的状态。状态检测电路被配置为便于基于二进制输出信号检测几种不同类型的输入电路。

3. 发明授权

US08463962B2 MAC and PHY interface arrangement 有权
标题翻译： MAC和PHY接口布置
公开(公告)号：US08463962B2
公开(公告)日：2013-06-11
申请号：US12377775
申请日：2007-08-01
申请人： Sharad Murari
发明人： Sharad Murari
IPC分类号： G06F13/12 , G06F13/38 , G06F13/42 , G06F13/14 , G06F13/36
CPC分类号： G06F13/385
摘要： According to an example embodiment of the present invention, a method is implemented for transmitting data between a Media Access Control Layer (MAC) (100) and a Physical Layer (PHY) (150) using an internal data bus for transmitting a set of internal symbols between the MAC (100) and PHY (150). A subset of internal symbols does not have a corresponding PHY symbol. An external data bus carries data symbols. An external interface (102, 118) provides command information on one or more dedicated command lines and provides the data symbols. An encoder (108, 110) encodes the provided command information into one or more of the subset of internal symbols. An internal interface (106, 107, 109, 111) transmits the one or more of the subset of internal symbols and the data symbols between the MAC (100) and PHY (150) using the internal data bus.
摘要翻译：根据本发明的示例实施例，实现了一种用于在介质访问控制层（MAC）（MAC）（PHY）（PHY）（PHY）（150））之间传输数据的方法，该内部数据总线用于传送一组内部 MAC（100）和PHY（150）之间的符号。内部符号的子集没有相应的PHY符号。外部数据总线承载数据符号。外部接口（102,118）提供关于一个或多个专用命令行的命令信息并提供数据符号。编码器（108,110）将所提供的命令信息编码成内部符号子集中的一个或多个。内部接口（106,107,109,111）使用内部数据总线在MAC（100）和PHY（150）之间传输内部符号子集和数据符号中的一个或多个。

4. 发明申请

US20130127512A1 MULTI-LEVEL CHIP INPUT 有权
标题翻译：多级芯片输入
公开(公告)号：US20130127512A1
公开(公告)日：2013-05-23
申请号：US13469704
申请日：2012-05-11
申请人： Sharad Murari
发明人： Sharad Murari
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K19/017509 , H03M1/0845 , H03M1/365
摘要： Aspects of the instant disclosure are directed toward apparatuses that generate a power-related adjustment signal in response to the power signal. Digital-input-signal pads are included to communicate digital signals with a circuit external to the apparatus. Further, digital-input processing circuitry receives the digital signals from the digital-input-signal pad, and processes the received digital signals. Additionally, configuration circuitry applies the power-related adjustment signal to signals received at the digital-input-signal pad and, in response, detects the digital signals received.
摘要翻译：本公开的方面涉及响应于功率信号产生与功率有关的调整信号的装置。包括数字输入信号焊盘以将数字信号与设备外部的电路进行通信。此外，数字输入处理电路从数字输入信号焊盘接收数字信号，并处理所接收的数字信号。此外，配置电路将功率相关调整信号应用于在数字输入信号焊盘处接收到的信号，并且作为响应，检测接收到的数字信号。

5. 发明授权

US08674726B2 Multi-level chip input circuit 有权
标题翻译：多级芯片输入电路
公开(公告)号：US08674726B2
公开(公告)日：2014-03-18
申请号：US13469704
申请日：2012-05-11
申请人： Sharad Murari
发明人： Sharad Murari
IPC分类号： H03K5/153
CPC分类号： H03L5/00 , H03K19/017509 , H03M1/0845 , H03M1/365
摘要： Aspects of the instant disclosure are directed toward apparatuses that generate a power-related adjustment signal in response to the power signal. Digital-input-signal pads are included to communicate digital signals with a circuit external to the apparatus. Further, digital-input processing circuitry receives the digital signals from the digital-input-signal pad, and processes the received digital signals. Additionally, configuration circuitry applies the power-related adjustment signal to signals received at the digital-input-signal pad and, in response, detects the digital signals received.
摘要翻译：本公开的方面涉及响应于功率信号产生与功率有关的调整信号的装置。包括数字输入信号焊盘以将数字信号与设备外部的电路进行通信。此外，数字输入处理电路从数字输入信号焊盘接收数字信号，并处理所接收的数字信号。此外，配置电路将功率相关调整信号应用于在数字输入信号焊盘处接收到的信号，并且作为响应，检测接收到的数字信号。

6. 发明申请

US20100315134A1 SYSTEMS AND METHODS FOR MULTI-LANE COMMUNICATION BUSSES 审中-公开
标题翻译：用于多通信通信总线的系统和方法
公开(公告)号：US20100315134A1
公开(公告)日：2010-12-16
申请号：US12867500
申请日：2009-03-02
申请人： Sharad Murari
发明人： Sharad Murari
IPC分类号： H03L7/00
CPC分类号： H04L7/0008 , H04L7/0012 , H04L7/0045 , H04L7/10
摘要： Multi-lane PCI express busses devices, methods and systems are implemented in various fashions. According to one such implementation, a method is used for synchronizing data transfers between IC dies of a plurality of integrated-circuits (IC) dies. In a first IC die, a synchronizing signal is received and latched in a first clock domain and in the first IC die to produce a first latched output signal. The latched output signal is provided for use by each of the plurality of IC dies. In each of the plurality of IC dies, the first latched output signal is latched in the first clock domain to produce a second latched output signal. The second latched output signal is latched in a second clock domain to produce a third latched output signal. The third latched output signal is used to synchronize a respective communication lane.
摘要翻译：多通道PCI Express总线设备，方法和系统以各种方式实现。根据一个这样的实施方式，使用一种方法来同步多个集成电路（IC）管芯的IC管芯之间的数据传输。在第一IC管芯中，同步信号被接收并锁存在第一时钟域和第一IC管芯中以产生第一锁存输出信号。锁存的输出信号被提供供多个IC芯片中的每一个使用。在多个IC管芯中的每一个中，第一锁存输出信号被锁存在第一时钟域中以产生第二锁存输出信号。第二锁存输出信号被锁存在第二时钟域中以产生第三锁存输出信号。第三锁存输出信号用于同步相应的通信通道。

7. 发明申请

US20100284451A1 MAC AND PHY INTERFACE ARRANGEMENT 有权
标题翻译： MAC和PHY接口布置
公开(公告)号：US20100284451A1
公开(公告)日：2010-11-11
申请号：US12377775
申请日：2007-08-01
申请人： Sharad Murari
发明人： Sharad Murari
IPC分类号： H04B1/38 , H04L27/00
CPC分类号： G06F13/385
摘要： According to an example embodiment of the present invention, a method is implemented for transmitting data between a Media Access Control Layer (MAC) (100) and a Physical Layer (PHY) (150) using an internal data bus for transmitting a set of internal symbols between the MAC (100) and PHY (150). A subset of internal symbols does not have a corresponding PHY symbol. An external data bus carries data symbols. An external interface (102, 118) provides command information on one or more dedicated command lines and provides the data symbols. An encoder (108, 110) encodes the provided command information into one or more of the subset of internal symbols. An internal interface (106, 107, 109, 111) transmits the one or more of the subset of internal symbols and the data symbols between the MAC (100) and PHY (150) using the internal data bus.
摘要翻译：根据本发明的示例实施例，实现了一种用于在介质访问控制层（MAC）（MAC）（PHY）（PHY）（PHY）（150））之间传输数据的方法，该内部数据总线用于传送一组内部 MAC（100）和PHY（150）之间的符号。内部符号的子集没有相应的PHY符号。外部数据总线承载数据符号。外部接口（102,118）提供关于一个或多个专用命令行的命令信息并提供数据符号。编码器（108,110）将所提供的命令信息编码成内部符号子集中的一个或多个。内部接口（106,107,109,111）使用内部数据总线在MAC（100）和PHY（150）之间传输内部符号子集和数据符号中的一个或多个。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式