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1. 发明授权

US06970024B1 Over-voltage protection of integrated circuit I/O pins 失效
标题翻译：集成电路I / O引脚的过电压保护
公开(公告)号：US06970024B1
公开(公告)日：2005-11-29
申请号：US10786370
申请日：2004-02-24
申请人： Dirk Reese , Tzung-Chin Chang , Chiakang Sung , Khai Nguyen , Gopinath Rangan , Xiaobao Wang
发明人： Dirk Reese , Tzung-Chin Chang , Chiakang Sung , Khai Nguyen , Gopinath Rangan , Xiaobao Wang
IPC分类号： H03K3/01 , H03K3/356 , H03K19/003
CPC分类号： H03K3/356113 , H03K19/00315
摘要： Circuits, methods, and apparatus for protecting devices in an output stage from over-voltage conditions caused by high supply and input voltages. Embodiments provide over-voltage protection that operates over a range of voltage levels, and that can be optimized for performance at different voltage levels. An exemplary embodiment of the present invention uses stacked devices to protect n and p-channel output devices from excess supply and input voltages. These stacked devices are biased by voltages received at their gates. These gate voltages vary as a function of supply voltage to maintain performance. Other embodiments of the present invention provide a body bias switch that generates a bias for the bulk of p-channel output devices. This bias tracks the higher of a supply or input voltage, such that parasitic drain-to-bulk diodes do not conduct. A switch may be provided that shorts the bulk connection to VCC under appropriate conditions.
摘要翻译：用于保护输出级的器件免受由高电源和输入电压引起的过电压状态的电路，方法和装置。实施例提供了在一定范围的电压电平上工作的过电压保护，并且可针对不同电压电平下的性能进行优化。本发明的示例性实施例使用堆叠器件来保护n和p沟道输出器件免受过多的电源和输入电压的影响。这些堆叠的器件被其栅极处接收的电压偏置。这些栅极电压随着电源电压而变化，以保持性能。本发明的其它实施例提供一种主体偏置开关，其产生用于大量p沟道输出装置的偏置。该偏置跟踪电源或输入电压的较高，使得寄生漏极 - 体二极管不导通。可以提供在适当条件下短路与VCC的大容量连接的开关。

2. 发明授权

US07215143B1 Input buffer for multiple differential I/O standards 有权
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US07215143B1
公开(公告)日：2007-05-08
申请号：US11000472
申请日：2004-11-29
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K19/094 , H03K19/0948 , H03K17/00
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

3. 发明授权

US07425844B1 Input buffer for multiple differential I/O standards 有权
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US07425844B1
公开(公告)日：2008-09-16
申请号：US11697299
申请日：2007-04-06
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K19/094 , H03K19/0948 , H03K17/00
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

4. 发明授权

US06911860B1 On/off reference voltage switch for multiple I/O standards 有权
标题翻译：用于多个I / O标准的开/关参考电压开关
公开(公告)号：US06911860B1
公开(公告)日：2005-06-28
申请号：US10037716
申请日：2001-11-09
申请人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Bonnie Wang , Philip Pan , Yan Chong , In Whan Kim , Gopinath Rangan , Tzung-Chin Chang
发明人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Bonnie Wang , Philip Pan , Yan Chong , In Whan Kim , Gopinath Rangan , Tzung-Chin Chang
IPC分类号： H03K17/35
CPC分类号： H03K17/6871 , H03K3/356113 , H03K17/063
摘要： A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.
摘要翻译：开关电路选择性地将某些I / O标准所需的参考电压提供给逻辑器件。该电路接收与设备的I / O电源不同的专用电源。其还可以包括电平移位电路，用于将具有由第一电源确定的逻辑电平的主控制信号转换成具有由专用电源确定的逻辑电平的第一控制信号。开关电路还包括传输开关，其响应于至少第一控制信号将参考电压传递到输出。传输开关可以是CMOS传输门，其中至少一个NMOS晶体管由第一控制信号控制，与由与第一控制信号互补的第二控制信号控制的至少一个PMOS晶体管并联。第二控制信号可以由另一电平移位电路产生并具有由I / O电源确定的逻辑电平。

5. 发明授权

US06731137B1 Programmable, staged, bus hold and weak pull-up for bi-directional I/O 有权
标题翻译：可编程，分段，总线保持和弱上拉双向I / O
公开(公告)号：US06731137B1
公开(公告)日：2004-05-04
申请号：US10131976
申请日：2002-04-24
申请人： Gopinath Rangan , Chiakang Sung , Xiaobao Wang , Philip Pan , Yan Chong , In Whan Kim , Khai Nguyen , Bonnie Wang , Tzung-Chin Chang , Joseph Huang
发明人： Gopinath Rangan , Chiakang Sung , Xiaobao Wang , Philip Pan , Yan Chong , In Whan Kim , Khai Nguyen , Bonnie Wang , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K3356
CPC分类号： H04L25/0264 , H03K5/08
摘要： The present invention encompasses a bus hold and weak pull-up circuit. A resistor having a first node and a second node is coupled to a bi-directional I/O pin at the first node. The weak pull-up circuit is directly coupled to the resistor at the first node. The bus hold circuit is coupled to the resistor at the second node.
摘要翻译：本发明包括总线保持和弱上拉电路。具有第一节点和第二节点的电阻器耦合到第一节点处的双向I / O引脚。弱上拉电路直接耦合到第一节点处的电阻器。总线保持电路耦合到第二节点处的电阻器。

6. 发明授权

US06870413B1 Schmitt trigger circuit with adjustable trip point voltages 有权
标题翻译：施密特触发电路具有可调跳闸点电压
公开(公告)号：US06870413B1
公开(公告)日：2005-03-22
申请号：US10017933
申请日：2001-12-14
申请人： Tzung-Chin Chang , Chiakang Sung , Khai Nguyen , Joseph Huang , Bonnie Wang , Yan Chong , Xiaobao Wang , Philip Pan , Gopinath Rangan , In Whan Kim
发明人： Tzung-Chin Chang , Chiakang Sung , Khai Nguyen , Joseph Huang , Bonnie Wang , Yan Chong , Xiaobao Wang , Philip Pan , Gopinath Rangan , In Whan Kim
IPC分类号： H03K3/3565 , H03K3/012
CPC分类号： H03K3/3565
摘要： A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and/or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.
摘要翻译：施密特触发电路具有可调滞后特性，通过提供多个反馈电路，其不同地影响电路的上跳点电平和较低跳变点电平的至少一个，优选两者。可以通过从第一组反馈电路中选择所需的反馈电路来调整上跳点电平，和/或可以通过从第二组反馈电路中选择所需的反馈电路来调整下跳变点电平。反馈电路选择由一个或多个可编程的控制信号来实现。可以调节滞后特性，以满足不同VCC电平下的所需噪声容限，延迟和输入识别准则。施密特触发电路可以是具有两个输入级NMOS，两个输入级PMOS晶体管，第一组NMOS反馈电路组和第二组PMOS反馈电路的CMOS施密特触发器。

7. 发明授权

US06825692B1 Input buffer for multiple differential I/O standards 有权
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US06825692B1
公开(公告)日：2004-11-30
申请号：US10056367
申请日：2002-01-25
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K190175
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

8. 发明授权

US06747903B1 Configurable decoder for addressing a memory 有权
标题翻译：用于寻址存储器的可配置解码器
公开(公告)号：US06747903B1
公开(公告)日：2004-06-08
申请号：US10046939
申请日：2002-01-14
申请人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong , Tzung-Chin Chang
发明人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong , Tzung-Chin Chang
IPC分类号： G11C700
CPC分类号： H03K19/1776 , G11C8/16
摘要： Methods and apparatus for decoding addresses in a memory to provide mixed input and output data widths. A method includes receiving an address portion comprising a first number of bits. A second number of bits of the address portion are blocked, where the second number is less than the first number. A third number of bits are not blocked, and the third number plus the second number equal the first number. The third number of bits are decoded and a fourth number of memory cells are selected. The fourth number is equal to two to the power of the second number. A fourth number of data bits are received and multiplexed to the selected memory cells. The data bits are written to the selected memory cells.
摘要翻译：用于解码存储器中的地址以提供混合的输入和输出数据宽度的方法和装置。一种方法包括接收包括第一位数的地址部分。地址部分的第二位数被阻塞，其中第二个数字小于第一个数字。第三个位数不被阻塞，第三个数字加上第二个数字等于第一个数字。第三位数被解码，并且选择第四数量的存储单元。第四个数字等于第二个数字的两倍。接收第四数量的数据位并将其多路复用到选择的存储单元。数据位被写入选定的存储单元。

9. 发明授权

US07218155B1 Techniques for controlling on-chip termination resistance using voltage range detection 有权
标题翻译：使用电压范围检测控制片上终端电阻的技术
公开(公告)号：US07218155B1
公开(公告)日：2007-05-15
申请号：US11040343
申请日：2005-01-20
申请人： Tzung-Chin Chang , Xiaobao Wang , Henry Kim , Chiakang Sung , Khai Q. Nguyen , Bonnie Wang , Jeffrey Tyhach , Gopinath Rangan
发明人： Tzung-Chin Chang , Xiaobao Wang , Henry Kim , Chiakang Sung , Khai Q. Nguyen , Bonnie Wang , Jeffrey Tyhach , Gopinath Rangan
IPC分类号： H03B1/00
CPC分类号： H03K19/0005
摘要： Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.
摘要翻译：提供了使用校准电路控制输入或输出（IO）缓冲器中的片上终端电阻的技术。校准电路监视外部电阻和片上晶体管组之间的电压。当外部电阻和晶体管组之间的电压在选定范围内时，校准电路会使晶体管的有效电阻尽可能接近外部电阻的电阻。校准电路使得IO缓冲器中的另一组晶体管能够使得IO缓冲器中的晶体管的有效导通电阻与外部电阻器的电阻紧密匹配。

10. 发明授权

US06731142B1 Circuit for providing clock signals with low skew 有权
标题翻译：提供低偏移时钟信号的电路
公开(公告)号：US06731142B1
公开(公告)日：2004-05-04
申请号：US10412705
申请日：2003-04-10
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
IPC分类号： H03K2100
CPC分类号： H03M9/00 , G06F1/08 , H03K5/135
摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.
摘要翻译：公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。延迟电路延迟输入参考时钟。在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。由于所有输出路径中的延迟相匹配，所以偏斜最小化。

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