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1. 发明授权

US09621908B2 Dynamic load balancing for video decoding using multiple processors 有权
公开(公告)号：US09621908B2
公开(公告)日：2017-04-11
申请号：US13602193
申请日：2012-09-02
申请人： Ding-Yun Chen , Cheng-Tsai Ho , Chi-Cheng Ju , Chung-Hung Tsai
发明人： Ding-Yun Chen , Cheng-Tsai Ho , Chi-Cheng Ju , Chung-Hung Tsai
IPC分类号： H04N19/436 , H04N19/61
CPC分类号： H04N19/436 , H04N19/61
摘要： A method and computer readable medium storing a corresponding computer program for decoding a video bitstream based on processors using dynamic load balancing are disclosed. In one embodiment of the present invention, the method configures multiple processors to perform the multiple processing modules including a prediction module by mapping the multiple processing modules to the multiple processors. One or more buffer queues are used among said multiple processing modules and the mapping the prediction module to the multiple processors is based on the level of the buffer queue. The multiple processors may correspond to a multi-core Central Processing Unit (CPU) comprising of multiple CPUs or a multi-core Digital Signal Processor (DSP) comprising of multiple DSPs to practice the present invention.

2. 发明申请

US20130058412A1 Dynamic Load Balancing for Video Decoding Using Multiple Processors 有权
标题翻译：使用多个处理器进行视频解码的动态负载平衡
公开(公告)号：US20130058412A1
公开(公告)日：2013-03-07
申请号：US13602193
申请日：2012-09-02
申请人： Ding-Yun Chen , Cheng-Tsai Ho , Chi-Cheng Ju , Chung-Hung Tsai
发明人： Ding-Yun Chen , Cheng-Tsai Ho , Chi-Cheng Ju , Chung-Hung Tsai
IPC分类号： H04N7/26 , H04N7/32
CPC分类号： H04N19/436 , H04N19/61
摘要： A method and computer readable medium storing a corresponding computer program for decoding a video bitstream based on processors using dynamic load balancing are disclosed. In one embodiment of the present invention, the method configures multiple processors to perform the multiple processing modules including a prediction module by mapping the multiple processing modules to the multiple processors. One or more buffer queues are used among said multiple processing modules and the mapping the prediction module to the multiple processors is based on the level of the buffer queue. The multiple processors may correspond to a multi-core Central Processing Unit (CPU) comprising of multiple CPUs or a multi-core Digital Signal Processor (DSP) comprising of multiple DSPs to practice the present invention.
摘要翻译：公开了一种基于使用动态负载平衡的处理器来存储用于解码视频位流的相应计算机程序的方法和计算机可读介质。在本发明的一个实施例中，该方法通过将多个处理模块映射到多个处理器来配置多个处理器来执行包括预测模块的多个处理模块。在所述多个处理模块中使用一个或多个缓冲器队列，并且基于缓冲器队列的级别将预测模块映射到多个处理器。多个处理器可以对应于包括多个CPU的多核心中央处理单元（CPU）或由多个DSP组成的多核数字信号处理器（DSP）来实施本发明。

3. 发明申请

US20070050685A1 METHOD OF RESETTING AN UNRESPONSIVE SYSTEM AND SYSTEM CAPABLE OF RECOVERING FROM AN UNRESPONSIVE CONDITION 审中-公开
标题翻译：重新设置不平衡系统的方法和能够从不平衡状态恢复的系统
公开(公告)号：US20070050685A1
公开(公告)日：2007-03-01
申请号：US11161948
申请日：2005-08-23
申请人： Chung-Hung Tsai
发明人： Chung-Hung Tsai
IPC分类号： G06F11/00
CPC分类号： G06F11/0757
摘要： A method of resetting an unresponsive system includes monitoring the system to detect when the system is in an unresponsive condition; receiving a predetermined code from a user interface; and resetting the system from the unresponsive condition after receiving the predetermined code from the user interface. In this way, a user of the system remains in control of resetting the system even when the system is otherwise unresponsive. For example, the user will notice that the system is not working properly and will perform a predetermined action on the user interface to thereby manually reset the system and regain control.
摘要翻译：重置无响应系统的方法包括监视系统以检测系统何时处于无响应状态; 从用户界面接收预定代码; 并且在从用户界面接收到预定代码之后，从无响应状态重置系统。以这种方式，即使系统没有响应，系统的用户仍然控制重置系统。例如，用户将注意到系统不能正常工作，并且将在用户界面上执行预定的动作，从而手动重置系统并重新获得控制。

4. 发明申请

US20050240706A1 Peripheral device control system 审中-公开
标题翻译：外围设备控制系统
公开(公告)号：US20050240706A1
公开(公告)日：2005-10-27
申请号：US11111510
申请日：2005-04-21
申请人： Chung-Hung Tsai
发明人： Chung-Hung Tsai
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4059
摘要： A peripheral device control system comprises a processor, a first bus, and a bridge device. The processor comprises a set of control instructions. The first bus couples to the processor by the first bus protocol. The bridge device communicates with the first bus by the first bus protocol and communicates with the peripheral device by a second protocol, wherein the processor transmits a set of control instructions to the peripheral device through the first bus and the bridge device, so as to directly control the peripheral device to perform a specific function.
摘要翻译：外围设备控制系统包括处理器，第一总线和桥接器件。处理器包括一组控制指令。第一个总线通过第一个总线协议耦合到处理器。桥接设备通过第一总线协议与第一总线进行通信，并通过第二协议与外围设备进行通信，其中处理器通过第一总线和桥接设备向外围设备发送一组控制指令，以便直接控制外围设备执行特定功能。

5. 发明授权

US08648739B2 Transmission interface and system using the same 有权
标题翻译：传输接口和系统使用相同
公开(公告)号：US08648739B2
公开(公告)日：2014-02-11
申请号：US12855595
申请日：2010-08-12
申请人： Wei-Cheng Ku , Chung-Hung Tsai , Chun-Nan Li , Yi-Hsi Chen
发明人： Wei-Cheng Ku , Chung-Hung Tsai , Chun-Nan Li , Yi-Hsi Chen
IPC分类号： H03M9/00
CPC分类号： H04N5/04 , G09G5/006 , G09G2370/10 , H04N21/43632
摘要： A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.
摘要翻译：传输接口包括第一引脚，第二引脚，转换单元和解码单元。转换单元经由第一引脚接收串行输入数据流，并经由第二引脚接收串行时钟。转换单元将串行输入数据流转换为并行输入数据，并将串行时钟转换为并行时钟。串行输入数据流具有全摆幅形式。解码单元接收和解码并行输入数据，并根据解码的并行输入数据生成输入数据信号。

6. 发明申请

US20120324152A1 MEMORY CONTROLLER WITH BI-DIRECTIONAL BUFFER FOR ACHIEVING HIGH SPEED CAPABILITY AND RELATED METHOD THEREOF 审中-公开
标题翻译：具有用于实现高速能力的双向缓冲器的存储器控制器及其相关方法
公开(公告)号：US20120324152A1
公开(公告)日：2012-12-20
申请号：US13593524
申请日：2012-08-24
申请人： Ming-Shiang Lai , Chung-Hung Tsai
发明人： Ming-Shiang Lai , Chung-Hung Tsai
IPC分类号： G06F12/02
CPC分类号： G06F13/1673
摘要： A memory controller for accessing a serial Flash memory is disclosed. The memory controller includes a logic circuit; a bi-directional buffer, coupled to the logic circuit, for selectively reversing the direction of data flow according to a control signal generated from the logic circuit, the bi-directional buffer comprising: an input port, coupled to a data output port of the logic circuit; a control port, coupled to the logic circuit, for receiving the control signal; and an output port, coupled to a data input port of the logic circuit, the output port being utilized for coupling both an input data port and an output data port of the serial Flash memory.
摘要翻译：公开了一种用于访问串行闪存的存储器控制器。存储器控制器包括逻辑电路; 耦合到逻辑电路的双向缓冲器，用于根据从逻辑电路产生的控制信号选择性地反转数据流的方向，所述双向缓冲器包括：输入端口，耦合到所述逻辑电路的数据输出端口逻辑电路; 耦合到所述逻辑电路的用于接收所述控制信号的控制端口; 以及耦合到逻辑电路的数据输入端口的输出端口，所述输出端口用于耦合串行闪存的输入数据端口和输出数据端口。

7. 发明申请

US20120038497A1 Transmission Interface and System Using the Same 有权
标题翻译：传输接口和系统使用相同
公开(公告)号：US20120038497A1
公开(公告)日：2012-02-16
申请号：US12855595
申请日：2010-08-12
申请人： Wei-Cheng Ku , Chung-Hung Tsai , Chun-Nan Li , Yi-Hsi Chen
发明人： Wei-Cheng Ku , Chung-Hung Tsai , Chun-Nan Li , Yi-Hsi Chen
IPC分类号： H03M9/00
CPC分类号： H04N5/04 , G09G5/006 , G09G2370/10 , H04N21/43632
摘要： A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.
摘要翻译：传输接口包括第一引脚，第二引脚，转换单元和解码单元。转换单元经由第一引脚接收串行输入数据流，并经由第二引脚接收串行时钟。转换单元将串行输入数据流转换为并行输入数据，并将串行时钟转换为并行时钟。串行输入数据流具有全摆幅形式。解码单元接收和解码并行输入数据，并根据解码的并行输入数据生成输入数据信号。

8. 发明授权

US07779399B2 System and method for securing web application code and verifying correctness of software 有权
标题翻译：用于保护Web应用程序代码和验证软件正确性的系统和方法
公开(公告)号：US07779399B2
公开(公告)日：2010-08-17
申请号：US11435232
申请日：2006-05-16
申请人： Yao-Wen Huang , Fang Yu , Chung-Hung Tsai , Christian Hang , Der-Tsai Lee , Sy-Yen Kuo
发明人： Yao-Wen Huang , Fang Yu , Chung-Hung Tsai , Christian Hang , Der-Tsai Lee , Sy-Yen Kuo
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F21/54
摘要： Methods, software tools and systems for analyzing software applications, e.g., Web applications, are described. A software application to be analyzed is transformed into an abstract representation which preserves its information flow properties. The abstract interpretation is evaluated to identify vulnerabilities using, for example, type qualifiers to associate security levels with variables and/or functions in the application being analyzed and typestate checking. Runtime guards are inserted into the application to secure identified vulnerabilities.
摘要翻译：描述用于分析软件应用（例如Web应用）的方法，软件工具和系统。要分析的软件应用程序被转换为保留其信息流特性的抽象表示。评估抽象解释以使用例如类型限定符来确定漏洞，以将安全级别与正在分析的应用程序中的变量和/或功能相关联并进行类型化检查。应用程序中插入运行时保护程序以确保已识别的漏洞。

9. 发明授权

US07743202B2 Command controller, prefetch buffer and methods for accessing a serial flash in an embedded system 有权
标题翻译：命令控制器，预取缓冲区和在嵌入式系统中访问串行闪存的方法
公开(公告)号：US07743202B2
公开(公告)日：2010-06-22
申请号：US11371423
申请日：2006-03-09
申请人： Chung-Hung Tsai , Ming-Shiang Lai
发明人： Chung-Hung Tsai , Ming-Shiang Lai
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/1004 , G06F2212/1016 , G06F2212/2022 , G06F2212/6022
摘要： The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.
摘要翻译：本发明涉及一种命令控制器和预取缓冲器，特别涉及用于访问嵌入式系统中的串行闪存的命令控制器和预取缓冲器。嵌入式系统包括串行闪存，处理器，多个访问设备以及预取缓冲器。处理器和多个访问设备发送各种命令以从串行闪存读取数据或向串行闪存写入数据。预取缓冲器在从串行闪存读取或写入数据之前临时存储预定量的数据。

10. 发明申请

US20080235412A1 MEMORY CONTROLLER WITH BI-DIRECTIONAL BUFFER FOR ACHIEVING HIGH SPEED CAPABILITY AND RELATED METHOD THEREOF 审中-公开
标题翻译：具有用于实现高速能力的双向缓冲器的存储器控制器及其相关方法
公开(公告)号：US20080235412A1
公开(公告)日：2008-09-25
申请号：US12125068
申请日：2008-05-22
申请人： Ming-Shiang Lai , Chung-Hung Tsai
发明人： Ming-Shiang Lai , Chung-Hung Tsai
IPC分类号： G06F13/00
CPC分类号： G06F13/1673
摘要： A memory controller for accessing a serial Flash memory is disclosed. The memory controller includes a logic circuit; a bi-directional buffer, coupled to the logic circuit, for selectively reversing the direction of data flow according to a control signal generated from the logic circuit, the bi-directional buffer comprising: an input port, coupled to a data output port of the logic circuit; a control port, coupled to the logic circuit, for receiving the control signal; and an output port, coupled to a data input port of the logic circuit, the output port being utilized for coupling both an input data port and an output data port of the serial Flash memory.
摘要翻译：公开了一种用于访问串行闪存的存储器控制器。存储器控制器包括逻辑电路; 耦合到逻辑电路的双向缓冲器，用于根据从逻辑电路产生的控制信号选择性地反转数据流的方向，所述双向缓冲器包括：输入端口，耦合到所述逻辑电路的数据输出端口逻辑电路; 耦合到所述逻辑电路的用于接收所述控制信号的控制端口; 以及耦合到逻辑电路的数据输入端口的输出端口，所述输出端口用于耦合串行闪存的输入数据端口和输出数据端口。

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