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1. 发明申请

US20140042591A1 CAPACITOR ARRANGEMENTS AND METHOD FOR MANUFACTURING A CAPACITOR ARRANGEMENT 有权
标题翻译：电容器布置和制造电容器布置的方法
公开(公告)号：US20140042591A1
公开(公告)日：2014-02-13
申请号：US13571453
申请日：2012-08-10
申请人： Dietrich Bonart
发明人： Dietrich Bonart
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/0805 , H01L27/0629 , H01L27/0811 , H01L29/1608 , H01L29/66181 , H01L29/861 , H01L29/872 , H01L29/93 , H01L29/94
摘要： In various embodiments, a capacitor arrangement is provided, which may include a substrate; a plurality of first doped regions and a plurality of second doped regions, wherein the first doped regions are doped with dopants of a first conductivity type and the second doped regions are doped with dopants of a second conductivity type being opposite to the first conductivity type, and wherein the plurality of first doped regions and the plurality of second doped regions are alternatingly arranged next to each other in the substrate; a dielectric layer disposed over the plurality of first doped regions and the plurality of second doped regions; an electrode disposed over the dielectric layer; a first terminal electrically coupled to each doped region of the plurality of first doped regions and the plurality of second doped regions; and a second terminal electrically coupled to the electrode.
摘要翻译：在各种实施例中，提供电容器布置，其可以包括基板; 多个第一掺杂区域和多个第二掺杂区域，其中所述第一掺杂区域掺杂有第一导电类型的掺杂剂，并且所述第二掺杂区域掺杂有与所述第一导电类型相反的第二导电类型的掺杂剂，并且其中所述多个第一掺杂区域和所述多个第二掺杂区域在所述衬底中彼此相邻地交替布置; 设置在所述多个第一掺杂区域和所述多个第二掺杂区域上的电介质层; 设置在电介质层上的电极; 电耦合到所述多个第一掺杂区域和所述多个第二掺杂区域中的每个掺杂区域的第一端子; 以及电耦合到所述电极的第二端子。

2. 发明申请

US20130320915A1 Gated Diode, Battery Charging Assembly and Generator Assembly 有权
标题翻译：门极二极管，电池充电组件和发电机组件
公开(公告)号：US20130320915A1
公开(公告)日：2013-12-05
申请号：US13484340
申请日：2012-05-31
申请人： Dirk Ahlers , Markus Zundel , Dietrich Bonart , Ludger Borucki
发明人： Dirk Ahlers , Markus Zundel , Dietrich Bonart , Ludger Borucki
IPC分类号： H01L29/78 , H02J7/00
CPC分类号： H01L29/7802 , H01L23/051 , H01L23/24 , H01L29/0634 , H01L29/0834 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/36 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H02J7/14 , H02J7/242 , H01L2924/00
摘要： A gated diode may include source zones and a drain zone which are both of a first conductivity type. The source zones directly adjoin a first surface of a semiconductor die and the drain zone directly adjoins an opposite second surface of the semiconductor die. The drain zone includes a drift zone formed in an epitaxial layer of the semiconductor die. Base zones of a second conductivity type, which is the opposite of the first conductivity type, are provided between the drain zones and the source zones. The drift zone further includes adjustment zones directly adjoining a base zone and arranged between the respective base zone and the second surface, respectively. A net dopant concentration in the adjustment zone is at least twice a net dopant concentration in the second sub-zone. The adjustment zones precisely define the reverse breakdown voltage.
摘要翻译：门控二极管可以包括源极区和漏极区，它们都是第一导电类型。源极区域直接邻接半导体管芯的第一表面，并且漏极区域直接邻接半导体管芯的相对的第二表面。漏区包括形成在半导体管芯的外延层中的漂移区。第二导电类型的与第一导电类型相反的基区设置在排水区和源区之间。漂移区还包括直接邻接基部区域并且分别布置在相应的基部区域和第二表面之间的调节区域。调整区域中的净掺杂剂浓度至少为第二子区域中的净掺杂剂浓度的两倍。调整区域精确定义反向击穿电压。

3. 发明申请

US20110256688A1 SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT 有权
公开(公告)号：US20110256688A1
公开(公告)日：2011-10-20
申请号：US13156970
申请日：2011-06-09
申请人： Andreas Meiser , Walter Hartner , Hermann Gruber , Dietrich Bonart , Thomas Gross
发明人： Andreas Meiser , Walter Hartner , Hermann Gruber , Dietrich Bonart , Thomas Gross
IPC分类号： H01L21/76
CPC分类号： H01L21/76802 , H01L21/76286 , H01L21/76877 , H01L21/84 , H01L27/1203
摘要： A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench.

4. 发明申请

US20060102946A1 Dynamic memory cell and method of manufacturing the same 审中-公开
标题翻译：动态存储单元及其制造方法
公开(公告)号：US20060102946A1
公开(公告)日：2006-05-18
申请号：US11325758
申请日：2006-01-05
申请人： Dietrich Bonart
发明人： Dietrich Bonart
IPC分类号： H01L29/94
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10891 , H01L29/66181 , H01L29/945
摘要： A memory device has a plurality of memory cells, wherein each memory cell has a trench capacitor formed in a semiconductor substrate and an access transistor for it. Each access transistor has a first contact region connected to an internal electrode of the trench capacitor, a second contact region to a bit line and a control electrode region, wherein the control electrode regions of neighboring access transistors are connected by a word line formed in the semiconductor substrate.
摘要翻译：存储器件具有多个存储单元，其中每个存储单元具有形成在半导体衬底中的沟槽电容器和用于其的存取晶体管。每个存取晶体管具有连接到沟槽电容器的内部电极，到位线的第二接触区域和控制电极区域的第一接触区域，其中相邻存取晶体管的控制电极区域通过形成在半导体衬底。

5. 发明授权

US09318485B2 Capacitor arrangements and method for manufacturing a capacitor arrangement 有权
标题翻译：用于制造电容器装置的电容器布置和方法
公开(公告)号：US09318485B2
公开(公告)日：2016-04-19
申请号：US13571453
申请日：2012-08-10
申请人： Dietrich Bonart
发明人： Dietrich Bonart
IPC分类号： H01L29/66 , H01L29/93 , H01L29/861 , H01L27/08 , H01L29/872 , H01L29/94 , H01L27/06 , H01L29/16
CPC分类号： H01L27/0805 , H01L27/0629 , H01L27/0811 , H01L29/1608 , H01L29/66181 , H01L29/861 , H01L29/872 , H01L29/93 , H01L29/94
摘要： In various embodiments, a capacitor arrangement is provided, which may include a substrate; a plurality of first doped regions and a plurality of second doped regions, wherein the first doped regions are doped with dopants of a first conductivity type and the second doped regions are doped with dopants of a second conductivity type being opposite to the first conductivity type, and wherein the plurality of first doped regions and the plurality of second doped regions are alternatingly arranged next to each other in the substrate; a dielectric layer disposed over the plurality of first doped regions and the plurality of second doped regions; an electrode disposed over the dielectric layer; a first terminal electrically coupled to each doped region of the plurality of first doped regions and the plurality of second doped regions; and a second terminal electrically coupled to the electrode.
摘要翻译：在各种实施例中，提供电容器布置，其可以包括基板; 多个第一掺杂区域和多个第二掺杂区域，其中所述第一掺杂区域掺杂有第一导电类型的掺杂剂，并且所述第二掺杂区域掺杂有与所述第一导电类型相反的第二导电类型的掺杂剂，并且其中所述多个第一掺杂区域和所述多个第二掺杂区域在所述衬底中彼此相邻地交替布置; 设置在所述多个第一掺杂区域和所述多个第二掺杂区域上的电介质层; 设置在电介质层上的电极; 电耦合到所述多个第一掺杂区域和所述多个第二掺杂区域中的每个掺杂区域的第一端子; 以及电耦合到所述电极的第二端子。

6. 发明授权

US07468307B2 Semiconductor structure and method 有权
标题翻译：半导体结构与方法
公开(公告)号：US07468307B2
公开(公告)日：2008-12-23
申请号：US11476497
申请日：2006-06-28
申请人： Walter Hartner , Andreas Meiser , Hermann Gruber , Dietrich Bonart , Thomas Gross
发明人： Walter Hartner , Andreas Meiser , Hermann Gruber , Dietrich Bonart , Thomas Gross
IPC分类号： H01L21/76
CPC分类号： H01L21/743 , H01L23/535 , H01L29/0653 , H01L29/7809 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.
摘要翻译：半导体结构包括半导体层堆叠，其包括第一导电类型的半导体衬底，第二导电类型的重掺杂掩埋层和形成在半导体层的顶部上的第三导电类型的单晶半导体层和埋入层，与埋层的接触，在接触孔中形成的接触以及半导体结构的不同部分的横向绝缘，所述绝缘体形成在隔离沟槽中。可以在隔离沟槽内形成与半导体衬底的接触。

7. 发明申请

US20070018195A1 Semiconductor structure and method 有权
标题翻译：半导体结构与方法
公开(公告)号：US20070018195A1
公开(公告)日：2007-01-25
申请号：US11476497
申请日：2006-06-28
申请人： Walter Hartner , Andreas Meiser , Hermann Gruber , Dietrich Bonart , Thomas Gross
发明人： Walter Hartner , Andreas Meiser , Hermann Gruber , Dietrich Bonart , Thomas Gross
IPC分类号： H01L29/74
CPC分类号： H01L21/743 , H01L23/535 , H01L29/0653 , H01L29/7809 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.
摘要翻译：半导体结构包括半导体层堆叠，其包括第一导电类型的半导体衬底，第二导电类型的重掺杂掩埋层和形成在半导体层的顶部上的第三导电类型的单晶半导体层和埋入层，与埋层的接触，在接触孔中形成的接触以及半导体结构的不同部分的横向绝缘，所述绝缘体形成在隔离沟槽中。可以在隔离沟槽内形成与半导体衬底的接触。

8. 发明授权

US06797562B2 Method for manufacturing a buried strap contact in a memory cell 失效
公开(公告)号：US06797562B2
公开(公告)日：2004-09-28
申请号：US10607033
申请日：2003-06-26
申请人： Dietrich Bonart , Gerhard Enders , Bjoern Fischer , Peter Voigt
发明人： Dietrich Bonart , Gerhard Enders , Bjoern Fischer , Peter Voigt
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10832
摘要： A method is provided for manufacturing a buried strap contact between a transistor and a trench capacitor in a memory cell, particularly a DRAM memory cell. In this method, the two spacers of the gate electrode lying opposite one another and the gate path applied on the trench insulation of the memory cell serve as part of the mask that is employed for etching the contact trench and in which the buried bridge of the trench capacitor is subsequently generated. As a result, the position of that sidewall of the bridge facing toward the gate electrode is generated in self-aligning fashion relative to the gate electrode. This avoids photolithographic tolerances in the positioning of the bridge relative to the gate electrode.

9. 发明授权

US09660550B2 Generator device for the voltage supply of a motor vehicle 有权
公开(公告)号：US09660550B2
公开(公告)日：2017-05-23
申请号：US13990334
申请日：2011-10-20
申请人： Richard Spitz , Alfred Goerlach , Carolin Tolksdorf , Dirk Ahlers , Dietrich Bonart
发明人： Richard Spitz , Alfred Goerlach , Carolin Tolksdorf , Dirk Ahlers , Dietrich Bonart
IPC分类号： H02M7/217 , H02M7/219 , H01L29/861 , H01L29/10 , H01L29/45 , H01L29/51 , H01L29/78
CPC分类号： H02M7/219 , H01L29/1095 , H01L29/456 , H01L29/51 , H01L29/7802 , H01L29/7813 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： A generator device for the voltage supply of a motor vehicle is equipped with at least one rectifying element for rectifying an alternating voltage provided by a generator. The rectifying element has an n-channel MOS field-effect transistor in which the gate, the body area, and the source area are electrically fixedly connected to one another and in which the drain area is used as a cathode.

10. 发明授权

US09324625B2 Gated diode, battery charging assembly and generator assembly 有权
标题翻译：门极二极管，电池充电组件和发电机组件
公开(公告)号：US09324625B2
公开(公告)日：2016-04-26
申请号：US13484340
申请日：2012-05-31
申请人： Dirk Ahlers , Markus Zundel , Dietrich Bonart , Ludger Borucki
发明人： Dirk Ahlers , Markus Zundel , Dietrich Bonart , Ludger Borucki
IPC分类号： H01L29/78 , H02J7/00 , H01L23/051 , H01L29/36 , H01L29/739 , H01L29/08 , H01L29/861 , H01L23/24 , H02J7/14
CPC分类号： H01L29/7802 , H01L23/051 , H01L23/24 , H01L29/0634 , H01L29/0834 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/36 , H01L29/7391 , H01L29/861 , H01L2924/0002 , H02J7/14 , H02J7/242 , H01L2924/00
摘要： A gated diode may include source zones and a drain zone which are both of a first conductivity type. The source zones directly adjoin a first surface of a semiconductor die and the drain zone directly adjoins an opposite second surface of the semiconductor die. The drain zone includes a drift zone formed in an epitaxial layer of the semiconductor die. Base zones of a second conductivity type, which is the opposite of the first conductivity type, are provided between the drain zones and the source zones. The drift zone further includes adjustment zones directly adjoining a base zone and arranged between the respective base zone and the second surface, respectively. A net dopant concentration in the adjustment zone is at least twice a net dopant concentration in the second sub-zone. The adjustment zones precisely define the reverse breakdown voltage.
摘要翻译：门控二极管可以包括源极区和漏极区，它们都是第一导电类型。源极区域直接邻接半导体管芯的第一表面，并且漏极区域直接邻接半导体管芯的相对的第二表面。漏区包括形成在半导体管芯的外延层中的漂移区。第二导电类型的与第一导电类型相反的基区设置在排水区和源区之间。漂移区还包括直接邻接基部区域并且分别布置在相应的基部区域和第二表面之间的调节区域。调整区域中的净掺杂剂浓度至少为第二子区域中的净掺杂剂浓度的两倍。调整区域精确定义反向击穿电压。

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