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1. 发明授权

US07480686B2 Method and apparatus for executing packed shift operations 有权
标题翻译：用于执行打包移位操作的方法和装置
公开(公告)号：US07480686B2
公开(公告)日：2009-01-20
申请号：US10846726
申请日：2004-05-14
申请人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Srinivas Chennupaty
发明人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Srinivas Chennupaty
IPC分类号： G06F5/01
CPC分类号： G06F7/762 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： A method and apparatus for performing a shift operation on packed data elements having multiple values. One embodiment includes accessing the shift control signal of a first format from a memory. The shift control signal identifyies a first packed shift operation and whether the shift positions are byte positions or bit positions, and causes a processor to execute a set of control signals of a second format, thereby accessing the packed data, shifting the packed data by the number of shift positions according to the first packed shift operation, generating a first replacement data for one of the number of positions, and producing a shifted first packed data comprising the first replacement data.
摘要翻译：一种用于对具有多个值的压缩数据元素执行移位操作的方法和装置。一个实施例包括从存储器访问第一格式的移位控制信号。移位控制信号识别第一打包移位操作以及移位位置是字节位置还是位位置，并使处理器执行一组第二格式的控制信号，从而访问打包数据，将打包数据移位根据第一打包移位操作的移位位置的数量，产生用于多个位置之一的第一替换数据，并且产生包括第一替换数据的移位的第一打包数据。

2. 发明授权

US06738793B2 Processor capable of executing packed shift operations 失效
标题翻译：能够执行打包移位操作的处理器
公开(公告)号：US06738793B2
公开(公告)日：2004-05-18
申请号：US09783816
申请日：2001-02-14
申请人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Srinivas Chennupaty
发明人： Derrick Chu Lin , Punit Minocha , Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Srinivas Chennupaty
IPC分类号： G06F505
CPC分类号： G06F7/762 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30167
摘要： An apparatus for performing a shift operation on a packed data element having multiple values. The apparatus having multiple muxes, each of the multiple muxes having a first input, a second input, a select input and an output. Each of the multiple bits that represent a shifted packed intermediate result on a first bus is coupled to the corresponding first input. Each of the multiple bits representing a replacement bit for one of the multiple values is coupled to a corresponding second input. Each of the multiple bits driven by a correction circuit is coupled to a corresponding select input. Each output corresponds to a bit of a shifted packed result.
摘要翻译：一种用于对具有多个值的压缩数据元素执行移位操作的装置。所述装置具有多个多路复用器，所述多个多路复用器中的每一个具有第一输入，第二输入，选择输入和输出。表示在第一总线上的移位的打包中间结果的多个比特中的每一个被耦合到对应的第一输入。表示多个值之一的替换位的多个比特中的每一个被耦合到对应的第二输入。由校正电路驱动的多个比特中的每一个被耦合到对应的选择输入。每个输出对应于移位包装结果的一位。

3. 发明申请

US20140189311A1 SYSTEM AND METHOD FOR PERFORMING A SHUFFLE INSTRUCTION 审中-公开
标题翻译：用于执行小指令的系统和方法
公开(公告)号：US20140189311A1
公开(公告)日：2014-07-03
申请号：US13732243
申请日：2012-12-31
申请人： Patrice Roussel , Srinivas Chennupaty , Michael Cranford , Mohammad Abdallah , James Coke , Katherine Kong
发明人： Patrice Roussel , Srinivas Chennupaty , Michael Cranford , Mohammad Abdallah , James Coke , Katherine Kong
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30032
摘要： An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.
摘要翻译：描述了使用计算机实现的步骤对打包数据执行洗牌操作的装置和方法。在一个实施例中，访问具有至少两个数据元素的第一打包数据操作数。具有至少两个数据元素的第二压缩数据操作数被访问。第一打包数据操作数中的数据元素之一被混洗到目的地寄存器的较低目的地字段中，并且第二打包数据操作数中的数据元素中的一个被混洗到目的地寄存器的上目的地字段中。

4. 发明申请

US20140032624A1 INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION 审中-公开
标题翻译：执行产品操作的指导和逻辑
公开(公告)号：US20140032624A1
公开(公告)日：2014-01-30
申请号：US14042681
申请日：2013-09-30
申请人： Ronen Zohar , Mark Seconi , Rajesh Parthasarathy , Srinivas Chennupaty , Mark Buxton , Chuck Desylva
发明人： Ronen Zohar , Mark Seconi , Rajesh Parthasarathy , Srinivas Chennupaty , Mark Buxton , Chuck Desylva
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F7/48 , G06F7/5443 , G06F9/3001
摘要： Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.
摘要翻译：用于执行点积运算的方法，装置和程序装置。在一个实施例中，一种装置包括执行第一指令的执行资源。响应于第一指令，所述执行资源存储到存储位置，结果值等于至少两个操作数的点积。

5. 发明授权

US07738484B2 Method, system, and apparatus for system level initialization 有权
标题翻译：用于系统级初始化的方法，系统和装置
公开(公告)号：US07738484B2
公开(公告)日：2010-06-15
申请号：US11011801
申请日：2004-12-13
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur N. Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur N. Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava
IPC分类号： H04L12/42
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

6. 发明申请

US20080077773A1 Instruction and logic for processing text strings 有权
标题翻译：用于处理文本字符串的指令和逻辑
公开(公告)号：US20080077773A1
公开(公告)日：2008-03-27
申请号：US11525981
申请日：2006-09-22
申请人： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
发明人： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
IPC分类号： G06F9/305
CPC分类号： G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
摘要： Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.
摘要翻译：用于执行字符串比较操作的方法，装置和程序装置。在一个实施例中，一种装置包括执行第一指令的执行资源。响应于第一指令，所述执行资源分别存储对应于第一和第二文本串的第一和第二操作数的每个数据元素之间的比较结果。

7. 发明申请

US20140344553A1 Gathering and Scattering Multiple Data Elements 审中-公开
标题翻译：收集和散布多个数据元素
公开(公告)号：US20140344553A1
公开(公告)日：2014-11-20
申请号：US13898189
申请日：2013-05-20
申请人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y.K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30036 , G06F9/30043 , G06F9/30145 , G06F9/345
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译：根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

8. 发明授权

US08787565B2 Method and apparatus for generating an advanced encryption standard (AES) key schedule 有权
标题翻译：用于生成高级加密标准（AES）密钥调度的方法和装置
公开(公告)号：US08787565B2
公开(公告)日：2014-07-22
申请号：US11841556
申请日：2007-08-20
申请人： Shay Gueron , Martin G. Dixon , Srinivas Chennupaty , Mayank Bomb , Brent R. Boswell
发明人： Shay Gueron , Martin G. Dixon , Srinivas Chennupaty , Mayank Bomb , Brent R. Boswell
IPC分类号： H04K1/00 , H04L9/00
CPC分类号： H04L9/28 , G06F9/30007 , H04L9/0631 , H04L2209/125 , H04L2209/24
摘要： An Advanced Encryption Standard (AES) key generation assist instruction is provided. The AES key generation assist instruction assists in generating round keys used to perform AES encryption and decryption operations. The AES key generation instruction operates independent of the size of the cipher key and performs key generation operations in parallel on four 32-bit words thereby increasing the speed at which the round keys are generated. This instruction is easy to use in software. Hardware implementation of this instruction removes potential threats of software (cache access based) side channel attacks on this part of the AES algorithm.
摘要翻译：提供了高级加密标准（AES）密钥生成辅助指令。 AES密钥生成辅助指令有助于生成用于执行AES加密和解密操作的循环密钥。 AES密钥生成指令独立于密码密钥的大小，并行执行四个32位字的密钥生成操作，从而增加生成循环密钥的速度。该指令在软件中易于使用。该指令的硬件实现可以消除这部分AES算法对软件（基于缓存访问的）侧面信道攻击的潜在威胁。

9. 发明申请

US20090265472A1 Method, System, and Apparatus for System Level Initialization 有权
标题翻译：用于系统级初始化的方法，系统和装置
公开(公告)号：US20090265472A1
公开(公告)日：2009-10-22
申请号：US12348723
申请日：2009-01-05
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddabaliapur Narasimha-Murthy Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava , Ioannis T. Schoinas
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddabaliapur Narasimha-Murthy Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava , Ioannis T. Schoinas
IPC分类号： G06F15/16 , G06F15/177
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

10. 发明授权

US07133040B1 System and method for performing an insert-extract instruction 失效
标题翻译：用于执行插入提取指令的系统和方法
公开(公告)号：US07133040B1
公开(公告)日：2006-11-07
申请号：US09053006
申请日：1998-03-31
申请人： Mohammad Abdallah , Srinivas Chennupaty , Robert S. Dreyer , Michael A. Julier , Katherine Kong , Larry Mennemeier , Ticky S. Thakkar
发明人： Mohammad Abdallah , Srinivas Chennupaty , Robert S. Dreyer , Michael A. Julier , Katherine Kong , Larry Mennemeier , Ticky S. Thakkar
IPC分类号： G06T15/00
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167
摘要： An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements is then accessed. The data element in the first data operand is inserted into any destination field of a destination register, or alternatively, a data element is extracted from any field of the source register.
摘要翻译：描述了使用计算机实现的步骤对打包数据执行插入 - 提取操作的装置和方法。在一个实施例中，访问具有数据元素的第一数据操作数。然后访问具有至少两个数据元素的第二打包数据操作数。将第一数据操作数中的数据元素插入到目的地寄存器的任何目的地字段中，或者替换地，从源寄存器的任何字段提取数据元素。

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