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1. 发明授权

US08427894B2 Implementing single bit redundancy for dynamic SRAM circuit with any bit decode 失效
标题翻译：用任意位解码实现动态SRAM电路的单位冗余
公开(公告)号：US08427894B2
公开(公告)日：2013-04-23
申请号：US12886692
申请日：2010-09-21
申请人： Derick G. Behrends , Todd A. Christensen , Peter T. Freiburger , Travis R. Hebig , Jayson K. Wittrup
发明人： Derick G. Behrends , Todd A. Christensen , Peter T. Freiburger , Travis R. Hebig , Jayson K. Wittrup
IPC分类号： G11C29/04 , G06F17/50
CPC分类号： G11C29/846
摘要： A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to a respective merged bit column select and redundancy steering multiplexer. Each merged bit column select and redundancy steering multiplexer receives a respective select signal input. A select signal generation circuit receives a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input.
摘要翻译：一种用于实现具有任何位解码的单位冗余的方法和动态静态随机存取存储器（SRAM）电路，以及提供主题电路所在的设计结构。 SRAM电路包括分别耦合到相应的合并位列选择和冗余转向多路复用器的多个位线列和一对冗余列。每个合并位列选择和冗余转向多路复用器接收相应的选择信号输入。选择信号发生电路接收冗余转向信号和相应的一个热位选择信号，产生相应的选择信号输入。

2. 发明申请

US20120069688A1 IMPLEMENTING SINGLE BIT REDUNDANCY FOR DYNAMIC SRAM CIRCUIT WITH ANY BIT DECODE 失效
标题翻译：用任意位解码器实现动态SRAM电路的单位冗余
公开(公告)号：US20120069688A1
公开(公告)日：2012-03-22
申请号：US12886692
申请日：2010-09-21
申请人： Derick G. Behrends , Todd A. Christensen , Peter T. Freiburger , Travis R. Hebig , Jayson K. Wittrup
发明人： Derick G. Behrends , Todd A. Christensen , Peter T. Freiburger , Travis R. Hebig , Jayson K. Wittrup
IPC分类号： G11C29/04 , G06F17/50
CPC分类号： G11C29/846
摘要： A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to a respective merged bit column select and redundancy steering multiplexer. Each merged bit column select and redundancy steering multiplexer receives a respective select signal input. A select signal generation circuit receives a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input.
摘要翻译：一种用于实现具有任何位解码的单位冗余的方法和动态静态随机存取存储器（SRAM）电路，以及提供主题电路所在的设计结构。 SRAM电路包括分别耦合到相应的合并位列选择和冗余转向多路复用器的多个位线列和一对冗余列。每个合并位列选择和冗余转向多路复用器接收相应的选择信号输入。选择信号发生电路接收冗余转向信号和相应的一个热位选择信号，产生相应的选择信号输入。

3. 发明授权

US08824196B2 Single cycle data copy for two-port SRAM 有权
标题翻译：双端口SRAM的单周期数据复制
公开(公告)号：US08824196B2
公开(公告)日：2014-09-02
申请号：US13435828
申请日：2012-03-30
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
IPC分类号： G11C11/00 , G06F17/50
CPC分类号： G06F17/505 , G11C11/412 , G11C11/419
摘要： A static random access memory (SRAM) includes a column of SRAM memory cells. The SRAM may include a circuit to copy a value stored in any SRAM memory cell in a column of SRAM memory cells to any SRAM memory cell in the column of SRAM memory cells in a single cycle of the SRAM.
摘要翻译：静态随机存取存储器（SRAM）包括一列SRAM存储单元。 SRAM可以包括电路，用于将存储在SRAM存储器单元的列中的任何SRAM存储器单元中的值复制到SRAM的单个周期中的SRAM存储单元列中的任何SRAM存储器单元。

4. 发明授权

US08578304B1 Implementing mulitple mask lithography timing variation mitigation 失效
标题翻译：实现多种掩模光刻时序变化缓解
公开(公告)号：US08578304B1
公开(公告)日：2013-11-05
申请号：US13558468
申请日：2012-07-26
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach
IPC分类号： G06F17/50
CPC分类号： G03F1/70
摘要： A method, system and computer program product are provided for implementing multiple mask lithography timing variation mitigation for a multiple mask polysilicon (PC) process. An application specific integrated circuit (ASIC) library includes at least one circuit device for a first mask, and at least one circuit device for a second mask. Critical hold time paths and critical setup time paths are identified in a circuit design. For critical hold time paths, circuit devices in the critical hold time paths are placed on a single mask of either the first mask or the second mask. For critical setup time paths, path delays are reduced by providing a mixture of circuit devices on the first mask and the second mask.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于实现多掩模多晶硅（PC）处理的多掩模光刻定时变化减轻。专用集成电路（ASIC）库包括用于第一掩模的至少一个电路装置和用于第二掩模的至少一个电路装置。在电路设计中标识临界保持时间路径和关键建立时间路径。对于临界保持时间路径，临界保持时间路径中的电路设备放置在第一掩模或第二掩模的单个掩模上。对于关键的建立时间路径，通过在第一掩模和第二掩模上提供电路装置的混合来减少路径延迟。

5. 发明申请

US20130175631A1 LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY 有权
标题翻译：布局以最小化小尺寸光刻机中的FET变化
公开(公告)号：US20130175631A1
公开(公告)日：2013-07-11
申请号：US13345439
申请日：2012-01-06
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
IPC分类号： H01L27/11 , H01L21/28 , G06F17/50
CPC分类号： H01L27/1104 , G11C5/025 , H01L21/28123 , H01L27/0207
摘要： A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.
摘要翻译：半导体芯片具有在足够小以至要求第一掩模和第二掩模的特定等级上的形状，第一掩模和第二掩模在处理期间分开曝光中使用。半导体芯片上的电路需要在第一和第二FET（场效应晶体管）之间的紧密跟踪。例如，特定级别可以是门形状级别。使用第一掩模和第二掩模的栅极形状的单独曝光将导致比仅由第一掩模限定的栅极形状的FET更差的FET跟踪（例如，栅极长度，阈值电压）。通过布置电路来选择性地提高FET跟踪，使得选择性FET由第一掩模限定。特别地，静态随机存取存储器（SRAM）设计受益于在SRAM单元中紧密跟踪六个或更多个FET。

6. 发明授权

US08344782B2 Method and apparatus to limit circuit delay dependence on voltage for single phase transition 失效
标题翻译：限制电路延迟依赖于单相电压的方法和装置
公开(公告)号：US08344782B2
公开(公告)日：2013-01-01
申请号：US12613673
申请日：2009-11-06
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
IPC分类号： H03H11/26
CPC分类号： H03K5/1534 , H03K5/133
摘要： A delay circuit receives a data input having an input transition and that generates a data output having an output transition. The delay circuit is powered by a voltage source having a voltage. A first delay element is configured to generate a first data signal with a first edge that has a relatively constant delay relative to the input transition irrespective of the voltage of the voltage source. A second delay element is configured to generate a second data signal with a second edge that has a delay relative to the input transition as a function of the voltage of the voltage source. A selection element causes the output transition at the data output to correspond to a latest selected one of the first edge and the second edge. The delay circuit may be employed in a pulse generating circuit.
摘要翻译：延迟电路接收具有输入转变的数据输入并产生具有输出转变的数据输出。延迟电路由具有电压的电压源供电。第一延迟元件被配置为产生第一数据信号，其中第一边缘相对于输入转换具有相对恒定的延迟，而与电压源的电压无关。第二延迟元件被配置为产生具有作为电压源的电压的函数的相对于输入转变的延迟的第二边缘的第二数据信号。选择元件使得数据输出处的输出转变对应于第一边缘和第二边缘中最新选择的一个。延迟电路可以用在脉冲发生电路中。

7. 发明授权

US08108739B2 High-speed testing of integrated devices 有权
标题翻译：集成设备的高速测试
公开(公告)号：US08108739B2
公开(公告)日：2012-01-31
申请号：US12110955
申请日：2008-04-28
申请人： Chad A. Adams , Derick G. Behrends , Todd A. Christensen , Travis R. Hebig
发明人： Chad A. Adams , Derick G. Behrends , Todd A. Christensen , Travis R. Hebig
IPC分类号： G11C29/30 , G11C29/50
CPC分类号： G11C29/48 , G11C11/41 , G11C29/12 , G11C29/1201 , G11C29/50012 , G11C2029/0401
摘要： A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device.
摘要翻译：一种用于允许具有用于存储数据的存储器单元的具有核的存储器件的高速可测试性的方法，包括：使得具有来自所述核的第一逻辑状态或第二逻辑状态的数据信号到达所述存储器件的输出端口在功能操作模式的评估周期内，并且在LBIST模式期间通过内置自检的阵列; 使得数据信号在LBIST模式期间能够在LBIST模式期间从与核心的数据信号在功能操作模式期间到达评估周期内的读取输出端口的最新可能时间一致的时刻改变为第一逻辑状态并通过自检内置的数组; 以及执行被配置为测试位于所述存储器件的传输路径下游的逻辑块的逻辑内置自检。

8. 发明授权

US07714630B2 Method and apparatus to limit circuit delay dependence on voltage 失效
标题翻译：限制电路延迟对电压的依赖性的方法和装置
公开(公告)号：US07714630B2
公开(公告)日：2010-05-11
申请号：US12138564
申请日：2008-06-13
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Daniel M. Nelson
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00026 , H03K2005/0013
摘要： The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an input voltage and two paths of inverters. At least two paths of inverters may be coupled to an input signal, the input signal may be low voltage (e.g. 0) or high voltage (e.g. 1). A first path may be referenced to a reference voltage while the second path may be referenced to the input voltage. The apparatus may include logic gates for receiving the output of each of the first path of inverters and the output of the second path of inverters to generate a desired output. As the input voltage increases, delay of the apparatus may decrease until the input voltage is approximately the same voltage as the reference voltage, at which the delay may remain constant.
摘要翻译：本公开是一种用于通过将输入电压增加到预定电压值来产生递减延迟的装置，在该点处延迟可以保持恒定。该装置可以包括电路，该电路包括接收输入电压的电压调节器和两个逆变器路径。反相器的至少两个路径可以耦合到输入信号，输入信号可以是低电压（例如0）或高电压（例如1）。第一路径可以参考参考电压，而第二路径可以参考输入电压。该装置可以包括逻辑门，用于接收每个逆变器的第一路径的输出和第二路径的反相器的输出以产生期望的输出。当输入电压增加时，装置的延迟可能减小，直到输入电压与参考电压大致相同的电压，在该电压处延迟可以保持恒定。

9. 发明申请

US20130258758A1 Single Cycle Data Copy for Two-Port SRAM 有权
标题翻译：双端口SRAM的单周期数据复制
公开(公告)号：US20130258758A1
公开(公告)日：2013-10-03
申请号：US13435828
申请日：2012-03-30
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach , Daniel M. Nelson
IPC分类号： G11C11/00 , G06F17/50
CPC分类号： G06F17/505 , G11C11/412 , G11C11/419
摘要： A static random access memory (SRAM) includes a column of SRAM memory cells. The SRAM may include a circuit to copy a value stored in any SRAM memory cell in a column of SRAM memory cells to any SRAM memory cell in the column of SRAM memory cells in a single cycle of the SRAM.
摘要翻译：静态随机存取存储器（SRAM）包括一列SRAM存储单元。 SRAM可以包括电路，用于将存储在SRAM存储器单元的列中的任何SRAM存储器单元中的值复制到SRAM的单个周期中的SRAM存储单元列中的任何SRAM存储器单元。

10. 发明申请

US20130222031A1 IMPLEMENTING POWER SAVING SELF POWERING DOWN LATCH STRUCTURE 有权
标题翻译：实现节能自卸机构结构
公开(公告)号：US20130222031A1
公开(公告)日：2013-08-29
申请号：US13404096
申请日：2012-02-24
申请人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach
发明人： Derick G. Behrends , Todd A. Christensen , Travis R. Hebig , Michael Launsbach
IPC分类号： H03K3/289
CPC分类号： H03K3/012 , H03K3/0375
摘要： A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal.
摘要翻译：一种用于实现省电自掉电锁存器操作的方法和电路，以及设置有该电路所在的设计结构。主从锁存器包括虚拟电源连接。至少一个连接控制装置耦合在虚拟电源连接和电压供应导轨之间。驱动器门施加驱动所述至少一个连接控制装置的掉电信号，以在自省电模式期间控制所述至少一个连接控制装置。驱动器门组合自省电输入信号和锁存数据输出信号以产生掉电信号。

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