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1. 发明授权

US06519283B1 Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphics 有权
标题翻译：具有多个视频源的集成视频处理系统，并具有屏幕显示图形的画中画
公开(公告)号：US06519283B1
公开(公告)日：2003-02-11
申请号：US09328756
申请日：1999-06-09
申请人： Dennis P. Cheney , Lawrence D. Curley , William R. Lee , Leland D. Richardson , Ronald S. Svec
发明人： Dennis P. Cheney , Lawrence D. Curley , William R. Lee , Leland D. Richardson , Ronald S. Svec
IPC分类号： H04B166
CPC分类号： H04N19/59 , H04N19/159 , H04N19/423 , H04N19/428 , H04N19/44 , H04N19/61
摘要： An integrated digital video system is configured to implement picture-in-picture merging of video signals from two or more video sources, as well as selective overlaying of on-screen display graphics onto the resultant merged signal. The picture-in-picture signal is produced for display by a television system otherwise lacking picture-in-picture capability. The digital video system can be implemented, for example, as an integrated decode system within a digital video set-top box or a digital video disc player. In one implementation, a decompressed digital video signal is downscaled and merged with an uncompressed video signal to produce the multi-screen display. The uncompressed video signal can comprise either analog or digital video. OSD graphics can be combined within the integrated system with the resultant multi-screen display or only with a received uncompressed analog video signal.
摘要翻译：集成数字视频系统被配置为实现来自两个或更多个视频源的视频信号的画中画合并，以及将屏幕显示图形选择性地覆盖到合成的合并信号上。画中画信号由电视系统产生，否则不具备画中画功能。数字视频系统可以例如实现为数字视频机顶盒或数字视频盘播放器内的集成解码系统。在一个实现中，解压缩的数字视频信号被缩小并与未压缩的视频信号合并以产生多屏显示。未压缩的视频信号可以包括模拟或数字视频。 OSD图形可以在集成系统中与最终的多画面显示相结合，或仅使用接收的未压缩模拟视频信号。

2. 发明授权

US06469743B1 Programmable external graphics/video port for digital video decode system chip 失效
标题翻译：可编程外部图形/视频端口，用于数字视频解码系统芯片
公开(公告)号：US06469743B1
公开(公告)日：2002-10-22
申请号：US09328757
申请日：1999-06-09
申请人： Dennis P. Cheney , Lawrence D. Curley , William R. Lee , Leland D. Richardson , Ronald S. Svec
发明人： Dennis P. Cheney , Lawrence D. Curley , William R. Lee , Leland D. Richardson , Ronald S. Svec
IPC分类号： H04N544
CPC分类号： H04N5/4401 , G09G5/363 , G09G2340/02 , G09G2340/125 , H04N9/641 , H04N21/426
摘要： A programmable bi-directional external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit is provided. The programmable EGV port employs a fixed number of signal input/output (I/O) pins on the video decode system chip while providing a plurality of connection configurations for an external graphics controller, an external digital display generator circuit and an external digital multi-standard decoder to the video decoder or the internal digital display generator circuit of the chip. The EGV port includes receiver/driver circuitry for accommodating in parallel a plurality of input/output signals, including pixel data signals and corresponding synchronization signals, as well as a programmable port controller adapted to be coupled between the receiver/driver circuitry and an internal bus of the video decode system allowing access to at least one of the video decoder and the internal digital display generator circuit. The programmable port controller is programmable to either receive data into the video decode system chip or to send data out from the video decode system chip.
摘要翻译：提供了一种用于具有视频解码器和内部数字显示发生器电路的视频解码系统芯片的可编程双向外部图形/视频（EGV）端口。可编程EGV端口在视频解码系统芯片上采用固定数量的信号输入/输出（I / O）引脚，同时为外部图形控制器，外部数字显示发生器电路和外部数字多路复用器提供多个连接配置，标准解码器到视频解码器或芯片的内部数字显示发生器电路。 EGV端口包括用于并行地并入包括像素数据信号和对应的同步信号的多个输入/输出信号的接收器/驱动器电路，以及适于耦合在接收器/驱动器电路和内部总线之间的可编程端口控制器的视频解码系统允许访问至少一个视频解码器和内部数字显示发生器电路。可编程端口控制器可编程为将数据接收到视频解码系统芯片中或从视频解码系统芯片发送数据。

3. 发明授权

US5430841A Context management in a graphics system 失效
标题翻译：图形系统中的上下文管理
公开(公告)号：US5430841A
公开(公告)日：1995-07-04
申请号：US968613
申请日：1992-10-29
申请人： David C. Tannenbaum , Paul M. Schanely , Leland D. Richardson , Bruce C. Hempel
发明人： David C. Tannenbaum , Paul M. Schanely , Leland D. Richardson , Bruce C. Hempel
IPC分类号： G06F3/14 , G06F3/048 , G06F9/46 , G06F9/48 , G06T17/00 , G06F12/00
CPC分类号： G06T17/00
摘要： A method and apparatus for the management of the data associated with multiple graphics contexts in a computer graphics rendering system. Graphics contexts are built by graphics engines and selectively saved into a context save RAM. Context switches are managed either by modifying a context base pointer to address a new section of the context save RAM, or by writing out a portion of the context save RAM to external storage and reading in a replacement context from external storage. The writing and reading process are managed by a control processor allowing the graphics engines to switch context at the same time. New contexts read from external storage automatically cause regeneration of downstream rasterization parameters.
摘要翻译：一种用于在计算机图形渲染系统中管理与多个图形上下文相关联的数据的方法和装置。图形上下文由图形引擎构建，并有选择地保存到上下文保存RAM中。上下文切换通过修改上下文基指针来处理上下文保存RAM的新部分，或者通过将外部存储RAM的一部分写入外部存储器并从外部存储器在替换上下文中读取来管理。写入和读取过程由控制处理器管理，允许图形引擎同时切换上下文。从外部存储器读取的新上下文会自动导致下游光栅化参数的再生。

4. 发明授权

US5434967A Decision variable hardware logic and processing methods for graphics display system 失效
标题翻译：图形显示系统的决策变量硬件逻辑和处理方法
公开(公告)号：US5434967A
公开(公告)日：1995-07-18
申请号：US967298
申请日：1992-10-27
申请人： David C. Tannenbaum , Andrew D. Bowen , Robert S. Horton , Leland D. Richardson , Paul M. Schanely
发明人： David C. Tannenbaum , Andrew D. Bowen , Robert S. Horton , Leland D. Richardson , Paul M. Schanely
IPC分类号： G09G5/393 , G06F15/16
CPC分类号： G09G5/393
摘要： Hardware logic and processing methods for enhanced data manipulation within a graphics display system are described. The graphics display system includes a graphics processor sub-system and a rendering subsystem which are serially connected for pipeline processing of an interleaved stream of commands and data. One or more status bits or XBITs are defined within each rasterizer of a multi-rasterizer rendering sub-system. An XBIT, which may comprise a ZBIT, a UBIT, or an RBIT, etc., provides a mechanism for introducing execution of various logic functions within the rendering sub-system portion of the computer graphics adapter. Corresponding data processing methods are also described.
摘要翻译：描述用于在图形显示系统内增强数据操作的硬件逻辑和处理方法。图形显示系统包括图形处理器子系统和呈现子系统，它们串行连接以用于交错的命令和数据流的流水线处理。在多光栅化渲染子系统的每个光栅化器内定义一个或多个状态位或XBIT。可以包括ZBIT，UBIT或RBIT等的XBIT提供用于在计算机图形适配器的渲染子系统部分内引入各种逻辑功能的执行的机制。还描述了相应的数据处理方法。

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