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    • 2. 发明授权
    • System and method for tracking infiniband RDMA read responses
    • 用于跟踪infiniband RDMA读取响应的系统和方法
    • US07620693B1
    • 2009-11-17
    • US10811557
    • 2004-03-29
    • James A. MottElisa Rodrigues
    • James A. MottElisa Rodrigues
    • G06F15/167G06F13/18
    • H04L49/9047H04L47/621H04L49/90H04L49/901H04L69/08H04L69/324
    • A system and method for tracking responses to InfiniBand RDMA Reads. When an RDMA Read or Read request is issued by a transmit module, a receive module is informed of the packet sequence numbers (PSN) associated with the expected RDMA Read responses. The receive module maintains a linked list for each queue pair that issues RDMA Reads. Each entry in the linked list corresponds to one RDMA Read for the associated queue pair, and identifies the first and last PSN and includes a link to the next entry in the linked list. When the final RDMA Read response is received, the receive module notifies the transmit module, which can then retire the RDMA Read from its retry queue.
    • 跟踪InfiniBand RDMA读取响应的系统和方法。 当发送模块发出RDMA读取或读取请求时,通知接收模块与预期RDMA读取响应相关联的数据包序列号(PSN)。 接收模块维护发出RDMA读取的每个队列对的链表。 链表中的每个条目对应于相关联的队列对的一个RDMA读取,并且识别第一个和最后一个PSN,并且包括链接到链表中的下一个条目。 当接收到最终的RDMA读取响应时,接收模块通知发送模块,然后发送模块可以从其重试队列中退出RDMA读取。
    • 3. 发明授权
    • Combined buffering of infiniband virtual lanes and queue pairs
    • infiniband虚拟通道和队列对的组合缓冲
    • US07327749B1
    • 2008-02-05
    • US10812254
    • 2004-03-29
    • James A. Mott
    • James A. Mott
    • H04L12/56
    • H04L47/30H04L47/10H04L49/90H04L49/9021
    • A system and method for shared buffering of InfiniBand virtual lanes and queue pairs. Instead of allocating dedicated memory space (e.g., a set of FIFO queues), a shared memory dynamically accommodates traffic received on different virtual lanes and/or queue pairs of an InfiniBand network. A multi-port RAM comprises memory buckets or elements for storing contents of InfiniBand packets. For each queue pair and/or virtual lane, matching head and tail pointers identify the first and last elements of a linked list of traffic buffered from that queue pair or virtual lane. A multi-port control structure mirrors the RAM. For each node in a queue pair or virtual lane's linked list, a corresponding entry in the control structure relates to the corresponding memory element and stores an identifier of the memory element and control entry corresponding to the next node in the linked list.
    • 用于InfiniBand虚拟通道和队列对的共享缓冲的系统和方法。 代替分配专用存储器空间(例如,一组FIFO队列),共享存储器动态地容纳在InfiniBand网络的不同虚拟通道和/或队列对上接收的业务。 多端口RAM包括存储桶或用于存储InfiniBand数据包的内容的元件。 对于每个队列对和/或虚拟通道,匹配的头和尾指针标识从该队列对或虚拟通道缓冲的流量的链表的第一个和最后一个元素。 多端口控制结构镜像RAM。 对于队列对或虚拟通道的链表中的每个节点,控制结构中的对应条目涉及对应的存储器元件,并且存储对应于链接列表中的下一个节点的存储器元素和控制条目的标识符。
    • 4. 发明授权
    • System for supplying multiple voltages to devices on circuit board through a sequencing in a predictable sequence
    • 通过可预测序列的顺序为电路板上的器件提供多个电压的系统
    • US06738915B1
    • 2004-05-18
    • US09569535
    • 2000-05-12
    • James A. MottWilliam M. Baldwin
    • James A. MottWilliam M. Baldwin
    • G06F126
    • G06F1/26H05K1/0254
    • An apparatus and method for enabling hot swapped circuit boards to receive multiple power voltages from a backplane and supply the multiple power voltages to devices on the circuit board in a predictable sequence. An apparatus according to the invention would include a circuit board having an electrical connector, a sequencing circuit, and an element. The electrical connector of the circuit board receives the multiple power voltages from another circuit board, such as a backplane or motherboard. The sequencing circuit receives the multiple power voltages from the electrical connector. When a part of the sequencing circuit receives a signal indicating that the sequencing circuit has received a first power voltage, the sequencing circuit provides a second power voltage to the element electrically coupled to the sequencing circuit.
    • 一种用于使热交换电路板从背板接收多个电源电压并以可预测的顺序将多个电源电压提供给电路板上的装置的装置和方法。 根据本发明的装置将包括具有电连接器,排序电路和元件的电路板。 电路板的电连接器从另一电路板(例如背板或主板)接收多个电源电压。 排序电路从电连接器接收多个电源电压。 当排序电路的一部分接收到指示排序电路已经接收到第一电源电压的信号时,排序电路向与排序电路电耦合的元件提供第二电源电压。
    • 6. 发明授权
    • System and method for interleaving infiniband sends and RDMA read responses in a single receive queue
    • 在单个接收队列中交织无限发送和RDMA读取响应的系统和方法
    • US07342934B1
    • 2008-03-11
    • US10811642
    • 2004-03-29
    • James A. MottElisa Rodrigues
    • James A. MottElisa Rodrigues
    • H04L12/56
    • H04L67/1097H04L49/901
    • A system and method for processing interleaved Sends of encapsulated communications and responses to RDMA Reads in a single InfiniBand queue pair receive queue. The queue is implemented as one or more linked lists of memory buckets, and stores Send commands (containing encapsulated communications or RDMA Read descriptors for retrieving a communication) until their associated communications are assembled and forwarded to a transmit module. The queue grows as new InfiniBand packets are received, and shrinks as communications (e.g., Ethernet packets) are forwarded. A next packet pointer identifies the next Send command whose communication should be assembled. If it is an encapsulated communication, the communication is forwarded. Otherwise, RDMA Read requests are issued and the responses bypass the tail of the queue and are assembled in an assembly area at the head of the queue.
    • 用于处理封装通信的交错发送和在单个InfiniBand队列对接收队列中对RDMA读取的响应的系统和方法。 队列被实现为存储器桶的一个或多个链表,并且存储发送命令(包含用于检索通信的封装通信或RDMA读描述符),直到其相关联的通信被组合并转发到发送模块。 当新的InfiniBand数据包被接收时,队列随着通信(例如,以太网数据包)被转发而收缩。 下一个分组指针标识下一个发送命令,其通信应该被组合。 如果是封装的通信,则转发通信。 否则,将发出RDMA读取请求,并且响应绕过队列的尾部,并组装在队列头部的装配区域中。
    • 7. 发明授权
    • System and method for infiniband receive flow control with combined buffering of virtual lanes and queue pairs
    • 用于虚拟信道的系统和方法通过虚拟通道和队列对的组合缓冲来接收流量控制
    • US07609636B1
    • 2009-10-27
    • US10812109
    • 2004-03-29
    • James A. Mott
    • James A. Mott
    • H04J3/14G06F11/00H04L12/54
    • H04L49/9047H04L49/90H04L49/9042H04L49/9078
    • A system and method for implementing flow control, at the link and/or transport layers, for InfiniBand receive traffic. A shared memory structure may be used for combined queuing of virtual lane and queue pair traffic. Each virtual lane is allocated a number of memory buffers; a packet is dropped if buffering it would cause its virtual lane to exceed its allocation of buffers. For each active queue pair, a linked list of buffers is maintained in the structure. Each queue pair is dedicated zero or more of its virtual lane's buffers, and may also use a set of buffers shared among multiple queue pairs. Thresholds are established in a queue pair's dedicated set of buffers and/or the shared set of buffers. As each threshold number of buffers is used, a queue pair can advertise fewer message credits. RNR-NAKs are issued when no more buffers are available to a queue pair.
    • 用于在链路和/或传输层处实现InfiniBand接收流量的流控制的系统和方法。 共享内存结构可用于虚拟通道和队列对流量的组合排队。 每个虚拟通道分配有多个内存缓冲区; 如果缓冲它会导致虚拟通道超过其缓冲区分配,则丢弃数据包。 对于每个活动队列对,在结构中维护缓冲区的链接列表。 每个队列对都是其虚拟通道的缓冲区的零个或多个,并且还可以使用在多个队列对之间共享的一组缓冲器。 阈值建立在队列对的专用缓冲器组和/或共享缓冲器组中。 当使用每个阈值数量的缓冲器时,队列对可以通告更少的消息信用。 当没有更多缓冲区可用于队列对时,发出RNR-NAK。
    • 9. 发明授权
    • Droplet placement onto surfaces
    • 液滴放置在表面上
    • US06814425B2
    • 2004-11-09
    • US10121352
    • 2002-04-12
    • James A. MottMark A. Van VeenMelissa Lee
    • James A. MottMark A. Van VeenMelissa Lee
    • B41J2145
    • B41J19/16
    • A method and apparatus for placing fluid droplets onto a surface in which at least one of a group of nozzles is substantially aligned with a first of parallel line segments on the surface moving in a first direction relative to the nozzles; at least one droplet is ejected from the first nozzle onto a target on the first segment; the group of nozzles is moved in a second direction having a component orthogonal to the first direction to respectively align first and second nozzles in the group with a second segment and with the first segment; the and fluid droplets are ejected from the nozzles onto targets on the segments, the center to center spacing of the targets along the segments equaling one or a multiple of the center to center spacing of the nozzles orthogonal to the segments.
    • 一种用于将流体液滴放置在表面上的方法和装置,其中一组喷嘴中的至少一个基本上与在相对于喷嘴沿第一方向移动的表面上的平行线段中的第一平行线段对准; 至少一个液滴从第一喷嘴喷射到第一段上的靶上; 所述喷嘴组在具有与所述第一方向正交的分量的第二方向上移动以分别对准所述组中的第一和第二喷嘴与第二部分和所述第一部分; 流体液滴从喷嘴喷射到分段上的目标上,目标沿着分段的中心到中心间隔等于与分段正交的喷嘴的中心到中心间距的一个或多个。
    • 10. 发明授权
    • Apparatus and method for testing for compatibility between circuit boards
    • 用于测试电路板之间兼容性的装置和方法
    • US06549027B1
    • 2003-04-15
    • US09707665
    • 2000-11-07
    • James A. Mott
    • James A. Mott
    • G01R104
    • H05K7/1445
    • An apparatus and method for comparing identifications of circuit boards in a midplane. When a first circuit board and a second circuit board are inserted into opposite sides of the midplane, an incompatibility between the first circuit board and the second circuit board may damage or impair the operation of one or both of the first circuit board and the second circuit board. To solve this problem, a first identification is stored on the first circuit board and a second identification is stored on the second circuit board. If the first identification of the first circuit board and the second identification of the second circuit board indicate an incompatibility, then one or both of the first circuit board and the second circuit board is/are prevented from fully powering up.
    • 一种用于比较中平面电路板标识的装置和方法。 当第一电路板和第二电路板插入中平面的相对侧时,第一电路板和第二电路板之间的不兼容性可能损坏或损害第一电路板和第二电路中的一个或两者的操作 板。 为了解决这个问题,第一识别被存储在第一电路板上,第二识别被存储在第二电路板上。 如果第一电路板的第一识别和第二电路板的第二识别指示不兼容,则第一电路板和第二电路板中的一个或两个被防止完全上电。