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1. 发明授权

US09069672B2 Extended fast memory access in a multiprocessor computer system 有权
标题翻译：在多处理器计算机系统中扩展快速存储器访问
公开(公告)号：US09069672B2
公开(公告)日：2015-06-30
申请号：US12483936
申请日：2009-06-12
申请人： Dennis C. Abts , Robert Alverson , Edwin Froese , Howard Pritchard , Steven L. Scott
发明人： Dennis C. Abts , Robert Alverson , Edwin Froese , Howard Pritchard , Steven L. Scott
IPC分类号： G06F12/08 , G06F12/10 , H04L29/08 , G06F9/38 , G06F13/40
CPC分类号： G06F15/167 , G06F9/3834 , G06F12/0813 , G06F12/1009 , G06F12/109 , G06F13/4009 , G06F2212/163 , H04L67/00
摘要： A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.
摘要翻译：多处理器计算机系统包括第一节点，用于通过从第一节点中的节点逻辑中的请求实体接收虚拟存储器地址来访问远程节点本地的存储器。第一节点从节点逻辑中接收的虚拟地址创建网络地址，其中网络地址处于比虚拟存储器地址更大的地址空间中，并且将快速存储器访问请求从第一节点发送到在网络地址。

2. 发明申请

US20100318626A1 EXTENDED FAST MEMORY ACCESS IN A MULTIPROCESSOR COMPUTER SYSTEM 有权
标题翻译：在多处理器计算机系统中扩展的快速存储器访问
公开(公告)号：US20100318626A1
公开(公告)日：2010-12-16
申请号：US12483936
申请日：2009-06-12
申请人： Dennis C. Abts , Robert Alverson , Edwin Froese , Howard Pritchard , Steven L. Scott
发明人： Dennis C. Abts , Robert Alverson , Edwin Froese , Howard Pritchard , Steven L. Scott
IPC分类号： G06F15/167 , G06F12/00 , G06F12/08
CPC分类号： G06F15/167 , G06F9/3834 , G06F12/0813 , G06F12/1009 , G06F12/109 , G06F13/4009 , G06F2212/163 , H04L67/00
摘要： A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.
摘要翻译：多处理器计算机系统包括第一节点，用于通过从第一节点中的节点逻辑中的请求实体接收虚拟存储器地址来访问远程节点本地的存储器。第一节点从节点逻辑中接收的虚拟地址创建网络地址，其中网络地址处于比虚拟存储器地址更大的地址空间中，并且将快速存储器访问请求从第一节点发送到在网络地址。

3. 发明授权

US08792512B2 Reliable message transport network 有权
标题翻译：可靠的消息传输网络
公开(公告)号：US08792512B2
公开(公告)日：2014-07-29
申请号：US11759748
申请日：2007-06-07
申请人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
发明人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/90 , H04L1/1607 , H04L1/1835 , H04L1/1874 , H04L1/188 , H04L2001/0096
摘要： A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.
摘要翻译：多处理器计算机系统包括发送处理器节点和接收处理器节点。所述发送处理器节点可操作以将包含消息的一部分的分组发送到接收机，以维护包括所发送的分组的所述发送方中的消息缓冲器条目，以跟踪已经接收到发送分组的来自所述接收机的确认; 以保持指示从消息数据发送起的时间的定时器，并且重新发送在定时器达到超时状态时未被确认的分组。接收处理器节点可操作以向接收到分组的发送方发送确认，以使用接收到的消息表来跟踪分组，以跟踪已经接收了包含消息的一部分的分组以及消息中的所有分组是否已被接收，并且一旦接收到消息中的所有分组以重新组合接收到的消息，则处理分组。

4. 发明授权

US08774203B2 One-way message notification with out-of-order packet delivery 有权
标题翻译：单程消息通知，具有无序包传送
公开(公告)号：US08774203B2
公开(公告)日：2014-07-08
申请号：US11759757
申请日：2007-06-07
申请人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
发明人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/90 , H04L1/0079 , H04L1/1635 , H04L1/188 , H04L47/10 , H04L47/34
摘要： A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, and to send a message complete packet after all packets in the message are sent. The message complete packet includes an indicator of the number of packets in the message, and the message is recognized as complete in the receiver once the number of packets indicated in the message complete packet have been received for the message. The sender tracks acknowledgment from the receiver of receipt of the sent packets; and notifies the receiver when it has received all packets comprising a part of the message.
摘要翻译：多处理器计算机系统包括发送处理器节点和接收处理器节点。发送处理器节点可操作以将包含消息的一部分的分组发送到接收机，并且在消息中的所有分组被发送之后发送消息完整分组。消息完成分组包括消息中的分组数量的指示符，并且一旦接收到该消息的消息完成分组中指示的分组数量，则该消息在接收机中被识别为完成。发送者跟踪接收到发送的数据包的确认; 并且当它接收到包括消息的一部分的所有分组时通知接收机。

5. 发明申请

US20080304491A1 RELIABLE MESSAGE TRANSPORT NETWORK 有权
标题翻译：可靠的信息传输网络
公开(公告)号：US20080304491A1
公开(公告)日：2008-12-11
申请号：US11759748
申请日：2007-06-07
申请人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
发明人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
IPC分类号： H04L12/28
CPC分类号： H04L49/90 , H04L1/1607 , H04L1/1835 , H04L1/1874 , H04L1/188 , H04L2001/0096
摘要： A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.
摘要翻译：多处理器计算机系统包括发送处理器节点和接收处理器节点。所述发送处理器节点可操作以将包含消息的一部分的分组发送到接收机，以维护包括所发送的分组的所述发送方中的消息缓冲器条目，以跟踪已经接收到发送分组的来自所述接收机的确认; 以保持指示从消息数据发送起的时间的定时器，并且重新发送在定时器达到超时状态时未被确认的分组。接收处理器节点可操作以向接收到分组的发送方发送确认，以使用接收到的消息表来跟踪分组，以跟踪已经接收了包含消息的一部分的分组以及消息中的所有分组是否已被接收，并且一旦接收到消息中的所有分组以重新组合接收到的消息，则处理分组。

6. 发明申请

US20080304479A1 ONE-WAY MESSAGE NOTIFICATOIN WITH OUT-OF-ORDER PACKET DELIVERY 有权
标题翻译：单向信息通知单与订单分发
公开(公告)号：US20080304479A1
公开(公告)日：2008-12-11
申请号：US11759757
申请日：2007-06-07
申请人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
发明人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L1/0079 , H04L1/1635 , H04L1/188 , H04L47/10 , H04L47/34
摘要： A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, and to send a message complete packet after all packets in the message are sent. The message complete packet includes an indicator of the number of packets in the message, and the message is recognized as complete in the receiver once the number of packets indicated in the message complete packet have been received for the message. The sender tracks acknowledgment from the receiver of receipt of the sent packets; and notifies the receiver when it has received all packets comprising a part of the message.
摘要翻译：多处理器计算机系统包括发送处理器节点和接收处理器节点。发送处理器节点可操作以将包含消息的一部分的分组发送到接收机，并且在消息中的所有分组被发送之后发送消息完整分组。消息完成分组包括消息中的分组数量的指示符，并且一旦接收到该消息的消息完成分组中指示的分组数量，则该消息在接收机中被识别为完成。发送者跟踪接收到发送的数据包的确认; 并且当它接收到包括消息的一部分的所有分组时通知接收机。

7. 发明授权

US08223778B2 Routing table architecture 有权
标题翻译：路由表架构
公开(公告)号：US08223778B2
公开(公告)日：2012-07-17
申请号：US11932457
申请日：2007-10-31
申请人： Steven L. Scott , Robert Alverson
发明人： Steven L. Scott , Robert Alverson
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , G06F11/0724 , G06F11/0781 , H04L45/40 , H04L45/54 , H04L45/60 , H04L45/742
摘要： A system and method for routing a packet between ports for use in a router having a plurality of ports, including a first and a second port, wherein each port includes a plurality of look-up tables (LUTs) and a look-up table select connected to the LUTs. Routing information is loaded into each of the plurality of LUTs while LUT selection information is loaded in the look-up table select. A packet having a plurality of destination bits is received at the first port and a destination port selected within the router to receive the packet. The destination port is selected by applying two or more of the destination bits to the plurality of LUTs in the first port and selecting an output of the plurality of LUTs as a function of one or more of the destination bits, wherein the selected output indicates the port selected to receive the packet. The packet is then routed to the output of the selected port.
摘要翻译：一种用于在具有包括第一和第二端口的多个端口的路由器中的端口之间路由分组的系统和方法，其中每个端口包括多个查找表（LUT）和查找表选择连接到LUT。路线信息被加载到多个LUT中的每一个中，而LUT选择信息被加载在查找表选择中。在第一端口处接收到具有多个目的地比特的分组，以及在路由器内选择的目的端口来接收分组。通过将两个或多个目的位应用于第一端口中的多个LUT并选择多个LUT的输出作为一个或多个目的地位的函数来选择目的地端口，其中所选择的输出指示选择端口接收数据包。然后将数据包路由到所选端口的输出。

8. 发明申请

US20100115234A1 CONFIGURABLE VECTOR LENGTH COMPUTER PROCESSOR 审中-公开
标题翻译：可配置矢量长度计算机处理器
公开(公告)号：US20100115234A1
公开(公告)日：2010-05-06
申请号：US12263302
申请日：2008-10-31
申请人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
发明人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F15/8053
摘要： A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.
摘要翻译：处理器核心包括一个或多个向量单元，其可操作以在具有较短最大向量长度的细粒子矢量模式和具有较长最大向量长度的粗粒矢量模式之间进行切换。更改向量模式包括停止核心中的所有指令流执行，刷新寄存器空间中的一个或多个寄存器，重新配置寄存器空间中的一个或多个向量寄存器，以及重新启动核心中的指令执行。

9. 发明授权

US08601236B2 Configurable vector length computer processor 有权
标题翻译：可配置向量长度计算机处理器
公开(公告)号：US08601236B2
公开(公告)日：2013-12-03
申请号：US13409033
申请日：2012-02-29
申请人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
发明人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
IPC分类号： G06F15/00
CPC分类号： G06F15/8053
摘要： A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.
摘要翻译：处理器核心包括一个或多个向量单元，其可操作以在具有较短最大向量长度的细粒子矢量模式和具有较长最大向量长度的粗粒矢量模式之间进行切换。更改向量模式包括停止核心中的所有指令流执行，刷新寄存器空间中的一个或多个寄存器，重新配置寄存器空间中的一个或多个向量寄存器，以及重新启动核心中的指令执行。

10. 发明授权

US08386750B2 Multiprocessor system having processors with different address widths and method for operating the same 有权
标题翻译：具有不同地址宽度的处理器的多处理器系统及其操作方法
公开(公告)号：US08386750B2
公开(公告)日：2013-02-26
申请号：US12263321
申请日：2008-10-31
申请人： Michael Parker , Timothy J. Johnson , Laurence S. Kaplan , Steven L. Scott , Robert Alverson , Skef Iterum
发明人： Michael Parker , Timothy J. Johnson , Laurence S. Kaplan , Steven L. Scott , Robert Alverson , Skef Iterum
IPC分类号： G06F12/08
CPC分类号： G06F12/0284
摘要： A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.
摘要翻译：多处理器计算机系统具有多个具有第一可寻址存储器空间的第一处理器和具有第二可寻址存储器空间的多个第二处理器。第二可寻址存储器空间的尺寸与第一可寻址存储器空间不同，并且第一可寻址存储器空间和第二可寻址存储器空间包括相同公共地址空间的一部分。

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