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1. 发明授权

US08149702B2 Multi-mode bit rate processor 有权
标题翻译：多模比特率处理器
公开(公告)号：US08149702B2
公开(公告)日：2012-04-03
申请号：US12199640
申请日：2008-08-27
申请人： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
发明人： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
IPC分类号： H04J1/16
CPC分类号： G06F15/7842 , H04L1/0045 , H04L1/0052 , H04L1/1829
摘要： An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.
摘要翻译：一种用于在无线系统中处理信号的装置包括用于从一组物理信道接收输入数据的第一存储器模块，用于处理输入数据的第一多个子模块。第一多个子模块中的每一个被选择为基于数据和传输信道规范起作用。该装置还包括用于接收经处理的输入数据和输出中间数据的第二存储器模块。第二存储器中的输入数据的位置与数据和传输通道规范相关联地被分配。该装置还包括用于处理中间数据的第二多个子模块。第二多个子模块中的每一个被选择为基于数据和传输信道规范起作用。该装置还包括用于接收和输出比特率处理输出的第三存储器模块。

2. 发明申请

US20090175205A1 Multi-mode Bit Rate Processor 有权
标题翻译：多模式比特率处理器
公开(公告)号：US20090175205A1
公开(公告)日：2009-07-09
申请号：US12199640
申请日：2008-08-27
申请人： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
发明人： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
IPC分类号： H04J1/00 , H04B7/216 , H04W88/02
CPC分类号： G06F15/7842 , H04L1/0045 , H04L1/0052 , H04L1/1829
摘要： An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.
摘要翻译：一种用于在无线系统中处理信号的装置包括用于从一组物理信道接收输入数据的第一存储器模块，用于处理输入数据的第一多个子模块。第一多个子模块中的每一个被选择为基于数据和传输信道规范起作用。该装置还包括用于接收经处理的输入数据和输出中间数据的第二存储器模块。第二存储器中的输入数据的位置与数据和传输通道规范相关联地被分配。该装置还包括用于处理中间数据的第二多个子模块。第二多个子模块中的每一个被选择为基于数据和传输信道规范起作用。该装置还包括用于接收和输出比特率处理输出的第三存储器模块。

3. 发明授权

US08316378B2 Data flow control in wireless communication systems 有权
标题翻译：无线通信系统中的数据流控制
公开(公告)号：US08316378B2
公开(公告)日：2012-11-20
申请号：US12254201
申请日：2008-10-20
申请人： John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
发明人： John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
IPC分类号： G06F9/44 , G06F15/16 , H04M1/64
CPC分类号： H04B1/71055 , H04B1/7105 , H04B2201/70711 , H04J13/0077
摘要： A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.
摘要翻译：一种方法包括在第一数据处理模块中接收数据，以及当接收到的数据的至少一个信号时隙包括符合第一数据传输标准的数据时启用第二数据处理模块。该方法还包括在第一数据处理模块和在处理器中执行的软件之间交换信号，以及确定第二数据处理模块的软件配置已经完成。该方法还包括处理第二数据处理模块中的至少一个信号时隙的数据，以及在完成对第二数据处理模块中的至少一个数据块的处理的完成时启用第三数据处理模块，并且确定第三数据处理模块的软件配置已经完成，所述至少一个数据块包括多个信号时隙。

4. 发明授权

US08054922B2 Parameter estimation for modulated signals 有权
标题翻译：调制信号的参数估计
公开(公告)号：US08054922B2
公开(公告)日：2011-11-08
申请号：US12189529
申请日：2008-08-11
申请人： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
发明人： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
IPC分类号： H04B1/10
CPC分类号： H04L27/34 , H04L27/3809
摘要： A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.
摘要翻译：系统包括用于接收调制信号的接收机。接收机包括用于将表示调制信号的星座点的复数数据转换为标量数据表示的增益估计器。增益估计器被配置为将标量数据表示的第一部分折叠到标量数据表示的第二部分上。增益估计器还被配置为从标量数据表示的折叠的第一部分和第二部分估计星座增益值。

5. 发明申请

US20090165019A1 Data Flow Control 有权
标题翻译：数据流控制
公开(公告)号：US20090165019A1
公开(公告)日：2009-06-25
申请号：US12254201
申请日：2008-10-20
申请人： John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
发明人： John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
IPC分类号： G06F9/46
CPC分类号： H04B1/71055 , H04B1/7105 , H04B2201/70711 , H04J13/0077
摘要： A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.
摘要翻译：一种方法包括在第一数据处理模块中接收数据，以及当接收到的数据的至少一个信号时隙包括符合第一数据传输标准的数据时启用第二数据处理模块。该方法还包括在第一数据处理模块和在处理器中执行的软件之间交换信号，以及确定第二数据处理模块的软件配置已经完成。该方法还包括处理第二数据处理模块中的至少一个信号时隙的数据，以及在完成对第二数据处理模块中的至少一个数据块的处理的完成时启用第三数据处理模块，并且确定第三数据处理模块的软件配置已经完成，所述至少一个数据块包括多个信号时隙。

6. 发明申请

US20090161745A1 Parameter Estimation for Modulated Signals 有权
标题翻译：调制信号的参数估计
公开(公告)号：US20090161745A1
公开(公告)日：2009-06-25
申请号：US12189529
申请日：2008-08-11
申请人： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
发明人： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
IPC分类号： H04B1/10 , H04B3/46
CPC分类号： H04L27/34 , H04L27/3809
摘要： A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.
摘要翻译：系统包括用于接收调制信号的接收机。接收机包括用于将表示调制信号的星座点的复数数据转换为标量数据表示的增益估计器。增益估计器被配置为将标量数据表示的第一部分折叠到标量数据表示的第二部分上。增益估计器还被配置为从标量数据表示的折叠的第一部分和第二部分估计星座增益值。

7. 发明申请

US20080080542A1 Architecture for downlink receiver bit rate processor 审中-公开
标题翻译：下行接收器比特率处理器的架构
公开(公告)号：US20080080542A1
公开(公告)日：2008-04-03
申请号：US11529148
申请日：2006-09-28
申请人： Krishnan Vishwanathan , Deepak Mathew , Eric Aardoom , Lidwine Martinot , Aiguo Yan , Timothy Fisher-Jeffes , Paul D. Krivacek
发明人： Krishnan Vishwanathan , Deepak Mathew , Eric Aardoom , Lidwine Martinot , Aiguo Yan , Timothy Fisher-Jeffes , Paul D. Krivacek
IPC分类号： H04L12/56
CPC分类号： H04B1/707 , H04L1/005 , H04L1/0052 , H04L1/0054 , H04L1/0067
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

8. 发明授权

US08358988B2 Interface between chip rate processing and bit rate processing in wireless downlink receiver 有权
标题翻译：无线下行接收机芯片速率处理与比特率处理之间的接口
公开(公告)号：US08358988B2
公开(公告)日：2013-01-22
申请号：US11529146
申请日：2006-09-28
申请人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
发明人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/7105 , H04B2201/70707
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级并且提供编码的传输信道数据。后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。

9. 发明申请

US20080081575A1 Re-Quantization in downlink receiver bit rate processor 有权
标题翻译：下行接收器比特率处理器中的重量化
公开(公告)号：US20080081575A1
公开(公告)日：2008-04-03
申请号：US11529071
申请日：2006-09-28
申请人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
发明人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/707 , H04L1/0045 , H04L1/0071
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

10. 发明授权

US08358987B2 Re-quantization in downlink receiver bit rate processor 有权
标题翻译：在下行链路接收机比特率处理器中重新量化
公开(公告)号：US08358987B2
公开(公告)日：2013-01-22
申请号：US11529071
申请日：2006-09-28
申请人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
发明人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/707 , H04L1/0045 , H04L1/0071
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级并且提供编码的传输信道数据。后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。

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