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1. 发明授权

US07865862B2 Design structure for dynamically selecting compiled instructions 有权
标题翻译：动态选择编译指令的设计结构
公开(公告)号：US07865862B2
公开(公告)日：2011-01-04
申请号：US11937106
申请日：2007-11-08
申请人： Deanna J. Chou , Jesse E. Craig , John Sargis, Jr. , Daneyand J. Singley , Sebastian T. Ventrone
发明人： Deanna J. Chou , Jesse E. Craig , John Sargis, Jr. , Daneyand J. Singley , Sebastian T. Ventrone
IPC分类号： G06F17/50
CPC分类号： G06F9/3836 , G06F9/3885
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于动态选择编译指令进行执行的装置，该装置包括用于接收用于在第一执行单元上执行的静态指令的输入，以及在第二执行单元上接收用于执行的动态指令执行单位以及指令选择元件，其适于基于所述执行单元的当前状态来评估所述静态指令和动态指令的吞吐量性能，并分别在所述第一执行单元或所述第二执行单元上的运行时选择所述静态指令或用于执行的所述动态指令，基于指令的吞吐量性能。

2. 发明授权

US07761690B2 Method, apparatus and computer program product for dynamically selecting compiled instructions 有权
标题翻译：用于动态选择编译指令的方法，装置和计算机程序产品
公开(公告)号：US07761690B2
公开(公告)日：2010-07-20
申请号：US11828705
申请日：2007-07-26
申请人： Deanna J. Chou , Jesse E. Craig , John Sargis, Jr. , Daneyand J. Singley , Sebastian T. Ventrone
发明人： Deanna J. Chou , Jesse E. Craig , John Sargis, Jr. , Daneyand J. Singley , Sebastian T. Ventrone
IPC分类号： G06F9/48
CPC分类号： G06F9/3836 , G06F9/3897 , G06F15/7867
摘要： A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.
摘要翻译：一种方法，装置和计算机程序产品动态地选择编译指令进行执行。接收用于在第一执行上执行的静态指令和用于在第二执行单元上执行的动态指令。基于执行单元的当前状态来评估静态指令和动态指令的吞吐量性能。基于指令的吞吐量性能，静态指令或动态指令分别被选择用于在运行时在第一执行单元或第二执行单元上执行。

3. 发明授权

US08595468B2 Reverse simultaneous multi-threading 失效
标题翻译：反向同步多线程
公开(公告)号：US08595468B2
公开(公告)日：2013-11-26
申请号：US12640112
申请日：2009-12-17
申请人： Shawn M. Luke , John Sargis, Jr. , Daneyand J. Singley
发明人： Shawn M. Luke , John Sargis, Jr. , Daneyand J. Singley
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3885 , G06F9/30181 , G06F9/3802 , G06F9/3828 , G06F9/3851
摘要： A multi-core processor system supporting simultaneous thread sharing across execution resources of multiple processor cores is provided. The multi-core processor system includes a first processor core with a first instruction queue and dispatch logic in communication with a first execution resource of the first processor core. The multi-core processor system also includes a second processor core with a second instruction queue and dispatch logic in communication with a second execution resource of the second processor core. A high-speed execution resource bus couples the first and second processor cores. The first instruction queue and dispatch logic is configured to issue a first instruction of a thread to the first execution resource and issue a second instruction of the thread over the high-speed execution resource bus to the second execution resource for simultaneous execution of the first and second instruction of the thread on the first and second processor cores.
摘要翻译：提供了支持跨多个处理器核心的执行资源同时进行线程共享的多核处理器系统。多核处理器系统包括具有第一指令队列的第一处理器核心和与第一处理器核心的第一执行资源通信的调度逻辑。多核处理器系统还包括具有第二指令队列的第二处理器核心和与第二处理器核心的第二执行资源通信的调度逻辑。高速执行资源总线耦合第一和第二处理器核心。第一指令队列和调度逻辑被配置为向第一执行资源发出线程的第一指令，并且通过高速执行资源总线向第二执行资源发出线程的第二指令，以同时执行第一和线程在第一和第二处理器核心上的第二条指令。

4. 发明授权

US08575964B2 Inactivity triggered self clocking logic family 有权
标题翻译：不活动触发自我计时逻辑家族
公开(公告)号：US08575964B2
公开(公告)日：2013-11-05
申请号：US13426776
申请日：2012-03-22
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , John Sargis, Jr. , Sebastian T. Ventrone , Charles S. Woodruff
IPC分类号： H03K19/00
CPC分类号： H03K19/0966 , H03K19/0013
摘要： Localized logic regions of a circuit include a local comparator electrically connected to a local resistive voltage circuit, to a local resistive ground circuit, and to a local register structure. The local comparator supplies a clock pulse to the local register structures when the local reference voltage is below a local voltage threshold. Activity in the local combinatorial logic structure causes the local reference voltage to drop below the local reference voltage independently of changes in the global reference voltage causing the comparator to output the clock pulse (with sufficient delay to allow the logic results to be stored in the registers only after setup times have been met in the local logic devices). This eliminates the need for a clock distribution tree, thereby saving power when there is no activity in the local combinatorial logic structure.
摘要翻译：电路的局部逻辑区域包括电连接到局部电阻电压电路的本地比较器，局部电阻接地电路和局部寄存器结构。当本地参考电压低于本地电压阈值时，本地比较器会向本地寄存器结构提供时钟脉冲。本地组合逻辑结构中的活动导致本地参考电压低于局部参考电压，而与全局参考电压的变化无关，导致比较器输出时钟脉冲（具有足够的延迟以允许逻辑结果存储在寄存器中只有在本地逻辑设备中已经满足设置时间之后）。这消除了对时钟分配树的需要，从而在局部组合逻辑结构中没有活动时节省功率。

5. 发明授权

US06980975B2 Method and apparatus for rule-based random irritator for model stimulus 失效
标题翻译：用于模型刺激的基于规则的随机刺激剂的方法和装置
公开(公告)号：US06980975B2
公开(公告)日：2005-12-27
申请号：US09998400
申请日：2001-11-15
申请人： Charlotte Anne Reed , John Sargis, Jr.
发明人： Charlotte Anne Reed , John Sargis, Jr.
IPC分类号： G01R31/3183 , G06F9/44 , G06F15/18 , G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357
摘要： For testing a logic unit under test (UUT), rule-based random irritation of a UUT model is provided to be used in conjunction with a simulator. The UUT model is stimulated (or irritated) with data patterns randomly generated by a pattern generator within the boundary of limitations imposed by a rules list. The rules list provides restrictions or encouragements on how data patterns are to be applied to the software model of the UUT. The pattern generator may be implemented either within or outside the simulator. If the pattern generator is incorporated into the simulator, then a software environment is required to interface communications between the pattern generator, the simulator, and other software entities involved in the simulation.
摘要翻译：为了测试被测逻辑单元（UUT），提供了与仿真器一起使用的基于UUT模型的基于规则的随机刺激。 UUT模型受到由规则列表强加的限制边界内的模式生成器随机生成的数据模式的刺激（或刺激）。规则列表对数据模式如何应用于UUT的软件模型提供了限制或鼓励。模式发生器可以在模拟器内部或外部实现。如果模式生成器被并入到模拟器中，那么需要一个软件环境来连接模式生成器，模拟器和模拟器中涉及的其他软件实体之间的通信。

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