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1. 发明授权

US06420278B1 Method for improving the dielectric constant of silicon-based semiconductor materials 失效
标题翻译：改善硅基半导体材料介电常数的方法
公开(公告)号：US06420278B1
公开(公告)日：2002-07-16
申请号：US09096760
申请日：1998-06-12
申请人： Dawn M. Hopper , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Richard J. Huang , Lu You
IPC分类号： H01L2131
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/3124
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials in which the dielectric constant has been reduced by spinning on the dielectric to silicon wafers, eliminating soft bake steps, and heating the wafers to about 400° C. for about one hour in a vacuum or inert atmosphere.
摘要翻译：通过使用硅基低介电常数材料制造超大规模集成电路，其中介电常数通过在电介质上旋转至硅晶片而减少，消除了软烘烤步骤，并将晶片加热至约400℃ 在真空或惰性气氛中约1小时。

2. 发明授权

US06136729A Method for improving semiconductor dielectrics 有权
标题翻译：改善半导体电介质的方法
公开(公告)号：US06136729A
公开(公告)日：2000-10-24
申请号：US133042
申请日：1998-08-12
申请人： Dawn M. Hopper , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Richard J. Huang , Lu You
IPC分类号： H01L21/312 , H01L21/314 , H01L21/316 , H01L21/31
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/3124 , H01L21/316
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric materials on a wafer in which the hydrophobic nature of the dielectric materials is improved by relative low temperature heating in a vacuum or inert atmosphere, slowly increasing the wafer temperature to the hard bake temperature at a predetermined ramp rate, and heating the wafer at the hard bake temperature for a predetermine amount of time. As a result, the dielectric material can repel wet etch chemicals and minimize the formation of holes in the dielectric materials due to etching by wet etch chemicals.
摘要翻译：通过在晶片上使用硅基低电介质材料制造超大规模集成电路，其中通过在真空或惰性气氛中的相对低温加热来提高电介质材料的疏水性，缓慢地将晶片温度提高到硬烘烤温度以预定的斜率进行，并且在硬烘烤温度下将晶片加热预定的时间量。结果，电介质材料可以排斥湿蚀刻化学品，并且由于通过湿蚀刻化学品的蚀刻使介电材料中的孔的形成最小化。

3. 发明授权

US06197703B1 Apparatus and method for manufacturing semiconductors using low dielectric constant materials 有权
标题翻译：使用低介电常数材料制造半导体的装置和方法
公开(公告)号：US06197703B1
公开(公告)日：2001-03-06
申请号：US09135077
申请日：1998-08-17
申请人： Lu You , Dawn M. Hopper , Richard J. Huang
发明人： Lu You , Dawn M. Hopper , Richard J. Huang
IPC分类号： H01L2131
CPC分类号： H01L21/02118 , H01L21/02134 , H01L21/02282 , H01L21/02362 , H01L21/312 , H01L21/3124 , Y10S438/913
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vapor deposition equipment, subject to chemical-mechanical polishing, and then processed by a conventional photolithographic process for depositing conductors. The material is then reprocessed for each successive layer of conductor separated by dielectric.
摘要翻译：通过使用硅基低介电常数材料制造超大规模集成电路，其在化学气相沉积设备中原位旋涂，干燥，固化和封盖。将低介电常数材料旋转，在化学气相沉积设备中进行处理，经受化学机械抛光，然后通过用于沉积导体的常规光刻工艺进行处理。然后对由电介质隔开的导体的每个连续层重新处理该材料。

4. 发明授权

US06388309B1 Apparatus and method for manufacturing semiconductors using low dielectric constant materials 有权
标题翻译：使用低介电常数材料制造半导体的装置和方法
公开(公告)号：US06388309B1
公开(公告)日：2002-05-14
申请号：US09687180
申请日：2000-10-12
申请人： Lu You , Dawn M. Hopper , Richard J. Huang
发明人： Lu You , Dawn M. Hopper , Richard J. Huang
IPC分类号： H01L2358
CPC分类号： H01L21/02118 , H01L21/02134 , H01L21/02282 , H01L21/02362 , H01L21/312 , H01L21/3124 , Y10S438/913
摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric constant materials which are spin-coated, dried, cured, and capped in-situ in chemical vapor deposition equipment. The low dielectric constant material is spun on, processed in chemical vapor deposition equipment, subject to chemical-mechanical polishing, and then processed by a conventional photolithographic process for depositing conductors. The material is then reprocessed for each successive layer of conductor separated by dielectric.
摘要翻译：通过使用硅基低介电常数材料制造超大规模集成电路，其在化学气相沉积设备中原位旋涂，干燥，固化和封盖。将低介电常数材料旋转，在化学气相沉积设备中进行处理，经受化学机械抛光，然后通过用于沉积导体的常规光刻工艺进行处理。然后对由电介质隔开的导体的每个连续层重新处理该材料。

5. 发明授权

US06518646B1 Semiconductor device with variable composition low-k inter-layer dielectric and method of making 有权
标题翻译：具有可变组成的低k层间电介质的半导体器件及其制造方法
公开(公告)号：US06518646B1
公开(公告)日：2003-02-11
申请号：US09819615
申请日：2001-03-29
申请人： Dawn M. Hopper , Suzette K. Pangrle , Calvin T. Gabriel , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Suzette K. Pangrle , Calvin T. Gabriel , Richard J. Huang , Lu You
IPC分类号： H01L2358
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76822 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Strong adhesion to doped low-k inter-layer dielectrics is provided by varying the composition of dopant near the surface layers of the inter-layer dielectric. The concentration of dopant is gradually increased from about zero atomic % at the interface between the inter-layer dielectric and semiconductor substrate to improve adhesion of the inter-layer dielectric to the semiconductor substrate. The concentration of dopant at the upper surface of the inter-layer dielectric is gradually decreased to about zero atomic % at the upper surface of the inter-layer dielectric film in order to improve adhesion of additional layers to the inter-layer dielectric.
摘要翻译：通过改变层间电介质的表面层附近掺杂剂的组成，提供了对掺杂低k层间电介质的强粘合性。掺杂剂的浓度在层间电介质和半导体衬底之间的界面处从约零原子％逐渐增加，以提高层间电介质与半导体衬底的粘合性。层间电介质的上表面的掺杂剂浓度在层间电介质膜的上表面逐渐降低至约零原子％，以提高附加层对层间电介质的附着力。

6. 发明授权

US06756672B1 Use of sic for preventing copper contamination of low-k dielectric layers 有权
标题翻译：使用sic来防止低k电介质层的铜污染
公开(公告)号：US06756672B1
公开(公告)日：2004-06-29
申请号：US09776750
申请日：2001-02-06
申请人： Lu You , Dawn M. Hopper , Suzette K. Pangrle
发明人： Lu You , Dawn M. Hopper , Suzette K. Pangrle
IPC分类号： H01L2348
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76804 , H01L21/76813 , H01L23/5222 , H01L23/5226 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from silicon carbide. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。通孔也可以有圆角。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层可以由碳化硅形成。还公开了制造半导体器件的方法。

7. 发明授权

US06576982B1 Use of sion for preventing copper contamination of dielectric layer 失效
标题翻译：使用硫化物防止介电层的铜污染
公开(公告)号：US06576982B1
公开(公告)日：2003-06-10
申请号：US09776746
申请日：2001-02-06
申请人： Lu You , Dawn M. Hopper , Minh Van Ngo
发明人： Lu You , Dawn M. Hopper , Minh Van Ngo
IPC分类号： H01L2358
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76804 , H01L21/76813 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from silicon oxynitride. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。通孔也可以有圆角。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层可以由氮氧化硅形成。还公开了制造半导体器件的方法。

8. 发明授权

US06677679B1 Use of SiO2/Sin for preventing copper contamination of low-k dielectric layers 有权
标题翻译：使用SiO2 / Sin来防止低k电介质层的铜污染
公开(公告)号：US06677679B1
公开(公告)日：2004-01-13
申请号：US09776749
申请日：2001-02-06
申请人： Lu You , Fei Wang , Dawn M. Hopper
发明人： Lu You , Fei Wang , Dawn M. Hopper
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76802 , H01L21/76804 , H01L21/76807 , H01L21/76831 , H01L21/76834
摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a second etch top layer, a dielectric layer and an opening extending through the dielectric layer, the first and second etch stop layers, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The second etch stop layer is disposed over the first diffusion barrier layer, and the first etch stop layer is disposed on the second etch stop layer with a first interface therebetween. The dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer and the barrier diffusion layer can be formed from silicon nitride, and the second etch stop layer can be formed from silicon oxide. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，第二蚀刻顶层，介电层和延伸穿过介电层的开口，第一和第二蚀刻停止层以及第一蚀刻停止层扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层上，并且第一蚀刻停止层设置在第二蚀刻停止层上，其间具有第一界面。介电层设置在第一蚀刻停止层上。开口也可以有圆角。侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层和阻挡扩散层可以由氮化硅形成，并且第二蚀刻停止层可以由氧化硅形成。开口内的金属形成第二金属特征，金属可以包括铜或铜合金。还公开了制造半导体器件的方法。

9. 发明授权

US06576545B1 Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-layer dielectrics and method of forming capping/ARC layers 有权
标题翻译：在氟掺杂石英玻璃层间电介质上具有双重性质封装/ ARC层的半导体器件和形成封盖/ ARC层的方法
公开(公告)号：US06576545B1
公开(公告)日：2003-06-10
申请号：US09819987
申请日：2001-03-29
申请人： Dawn M. Hopper , Lu You , Minh Van Ngo
发明人： Dawn M. Hopper , Lu You , Minh Van Ngo
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/76807
摘要： Degradation of fluorine-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on a fluorine-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.
摘要翻译：通过在层间电介质膜上形成双重性能覆盖/ ARC层，制造过程中氟掺杂二氧化硅玻璃低k层间电介质的退化显着降低，亚微米特征的分辨率得到改善。封盖/ ARC层在氟掺杂石英玻璃层间电介质上原位形成。封盖/ ARC层的原位形成提供了强烈粘附的封盖/ ARC层，其形成与传统封盖和ARC层相比较少的处理步骤。

10. 发明授权

US06713874B1 Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics 有权
标题翻译：在有机掺杂的石英玻璃层间电介质上具有双重自然封盖/电弧层的半导体器件
公开(公告)号：US06713874B1
公开(公告)日：2004-03-30
申请号：US09817050
申请日：2001-03-27
申请人： Dawn M. Hopper , Lu You , Minh Van Ngo
发明人： Dawn M. Hopper , Lu You , Minh Van Ngo
IPC分类号： H01L2348
CPC分类号： H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L23/3171 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Degradation of organic-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on the organic-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.
摘要翻译：通过在层间电介质膜上形成双重性质覆盖/ ARC层，在制造期间降低有机掺杂石英玻璃低k层间电介质的降解显着降低，并提高亚微米特征的分辨率。在有机掺杂的石英玻璃层间电介质上原位形成封盖/ ARC层。封盖/ ARC层的原位形成提供了强烈粘附的封盖/ ARC层，其形成与传统封盖和ARC层相比较少的处理步骤。

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