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1. 发明授权

US07890561B2 Random number generator 失效
标题翻译：随机数发生器
公开(公告)号：US07890561B2
公开(公告)日：2011-02-15
申请号：US11204402
申请日：2005-08-16
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： G06F1/02 , G06F7/58
CPC分类号： G06F7/588 , H04L9/001 , H04L9/0869
摘要： A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.
摘要翻译：提供随机数生成器，方法和计算机程序产品用于产生随机数种子。振荡器阵列内的每个振荡器以不同的频率工作。每个振荡器的工作频率不是谐波相关的，使得在任何两个振荡器的频率之间不存在整数倍。在一个实施例中，振荡器阵列的输出连接到多输入锁存器。多输入锁存器还接收作为时钟信号的采样信号。时钟信号对振荡器阵列的输出采样，并且多输入锁存器与随机数确定逻辑（“RNDL”）一起为阵列内的每个振荡器产生数字输出（0或1）。 RNDL使用这些数字输出创建一个随机数字种子。

2. 发明授权

US07279996B2 Method of functionality testing for a ring oscillator 失效
公开(公告)号：US07279996B2
公开(公告)日：2007-10-09
申请号：US11204408
申请日：2005-08-16
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K5/133
摘要： A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input. The embodiment further comprises detecting the response to the applied first and second test bit signals at the output of the second inverter, and using the detected responses in providing an evaluation of functionality of the ring oscillator.

3. 发明授权

US07233212B2 Oscillator array with row and column control 有权
标题翻译：具有行和列控制的振荡器阵列
公开(公告)号：US07233212B2
公开(公告)日：2007-06-19
申请号：US11095895
申请日：2005-03-31
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： H03B29/00 , H03K3/03
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.
摘要翻译：提供了一种电路拓扑结构，可用于创建由通用控制输入确定的不同频率运行的单独调谐的振荡器阵列，以及易于管理的多个组件的设计尺寸变化。提供了一列列和列排列的振荡器阵列。列中的每个振荡器都基于列中的其他振荡器是独特的，基于振荡器和扇出的级数，使得每个振荡器将以唯一的频率工作。阵列中不同列的振荡器可能会通过对这些振荡器的选择的共同设置以及列中的振荡器的物理顺序而不同，以进一步降低注入锁定的可能性。基本延迟单元为每列振荡器提供选择，使得每列可被编程为以与其邻居不同的频率工作。

4. 发明授权

US06760819B2 Symmetric multiprocessor coherence mechanism 有权
标题翻译：对称多处理器一致性机制
公开(公告)号：US06760819B2
公开(公告)日：2004-07-06
申请号：US09895888
申请日：2001-06-29
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty , Thuong Quang Truong
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty , Thuong Quang Truong
IPC分类号： G06F1208
CPC分类号： G06F12/0822 , G06F12/0811 , G06F12/084
摘要： A processor-cache operational scheme and topology within a multi-processor data processing system having a shared lower level cache (or memory) by which the number of coherency busses is reduced and more efficient snoop resolution and coherency operations with the processor caches are provided. A copy of the internal (L1) cache directory is provided within the lower level (L2) cache or memory. The snoop operations and coherency maintenance operations of the L1 directory are completed by comparing the snoop addresses with the address tags of the copy of the L1 directory in the L2 cache. Updates to the coherency states of the copy of the L1 directory are mirrored in the L1 directory and L1 cache. This eliminates the need for the individual coherency buses of each processor that is coupled to the L2 cache and speeds up coherency operations because the snoops do not have to be transmitted to the L1 caches.
摘要翻译：提供具有共享低级高速缓存（或存储器）的多处理器数据处理系统中的处理器 - 高速缓存操作方案和拓扑，通过该共享低级高速缓存（或存储器）减少一致性总线的数量并且提供与处理器高速缓存更有效的窥探分辨率和一致性操作。在低级（L2）高速缓存或内存中提供内部（L1）缓存目录的副本。通过将侦听地址与L2缓存中L1目录的副本的地址标签进行比较，完成L1目录的侦听操作和一致性维护操作。对L1目录的副本的一致性状态的更新被镜像在L1目录和L1缓存中。这消除了对耦合到L2高速缓存的每个处理器的各个一致性总线的需要，并且加速一致性操作，因为该探测不必被传送到L1高速缓存。

5. 发明授权

US08838950B2 Security architecture for system on chip 有权
标题翻译：片上系统的安全架构
公开(公告)号：US08838950B2
公开(公告)日：2014-09-16
申请号：US10601374
申请日：2003-06-23
申请人： David John Craft , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
发明人： David John Craft , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
IPC分类号： G06F21/00 , H04L9/32 , G06F21/53
CPC分类号： G06F21/53 , H04L9/3226 , H04L2209/56
摘要： The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.
摘要翻译：本发明提供了验证代码和/或数据并提供受保护的环境以供执行。本发明提供了用于对代码或数据的认证的动态分区和分区本地存储。本地商店被划分成一个隔离和非隔离的部分。代码或数据被加载到隔离的部分。代码或数据在本地存储的隔离部分进行身份验证。认证后，执行代码。在执行之后，附着的处理器单元的隔离区域内的存储器被擦除，并且附加的处理器单元对本地存储器内的隔离部分进行分区。

6. 发明授权

US07836222B2 System and method for tracking messages between a processing unit and an external device 有权
标题翻译：用于跟踪处理单元和外部设备之间的消息的系统和方法
公开(公告)号：US07836222B2
公开(公告)日：2010-11-16
申请号：US10606582
申请日：2003-06-26
申请人： Michael Norman Day , Brian King Flachs , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
发明人： Michael Norman Day , Brian King Flachs , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
IPC分类号： G06F3/00 , G11C8/00
CPC分类号： H04Q3/545 , H04Q2213/13106
摘要： An apparatus which uses channel counters in combination with channel count read instructions as a means of providing information that data in a given channel is valid or has not been previously read. The counter may also, in the situation of the channel being defined as blocking, be used to prevent the unintentional overwriting of data in a register used by the channel or, alternatively, prevent further communications with the device assigned to that channel when a given count occurs. Intelligent external devices may also use channel count read instructions sent to the counting mechanism for reading from and writing to the channel.
摘要翻译：使用信道计数器与信道计数读取指令组合的装置作为提供给定信道中的数据有效或先前未被读取的信息的手段。在信道被定义为阻塞的情况下，计数器还可以用于防止在信道使用的寄存器中无意中覆盖数据，或者替代地，当给定计数时，防止与分配给该信道的设备的进一步通信发生。智能外部设备还可以使用发送到计数机构的通道计数读取指令来读取和写入通道。

7. 发明授权

US07197655B2 Lowered PU power usage method and apparatus 失效
标题翻译：降低PU功率使用方法和装置
公开(公告)号：US07197655B2
公开(公告)日：2007-03-27
申请号：US10606581
申请日：2003-06-26
申请人： Brian King Flachs , John Samuel Liberty , Harm Peter Hofstee
发明人： Brian King Flachs , John Samuel Liberty , Harm Peter Hofstee
IPC分类号： G06F1/00
CPC分类号： G06F1/3209
摘要： Disclosed is an apparatus which places computer program instructions into instruction channels in accordance with predefined criteria such that at least some external event instructions are placed in a special “blocking channel.” The number of instructions, in a channel, is monitored in channel specific counters. When a computer processor is awaiting a response from an external entity event (in other words, is blocked from proceeding with the operation the PU is attempting), as signified by the blocking counter being at a predetermined value, the entire PU or at least processor auxiliary components that would be idle, such as math logic, while awaiting an external event response, are deactivated to save power until an awaited external event response is received.
摘要翻译：公开了一种根据预定准则将计算机程序指令置于指令通道中的装置，使得至少一些外部事件指令被放置在特殊的“阻塞通道”中。在通道特定计数器中监视通道中的指令数。当计算机处理器正在等待来自外部实体事件的响应（换句话说，阻止PU正在尝试的操作），如由阻塞计数器所指示的，处于预定值，整个PU或至少处理器在等待外部事件响应的情况下，诸如数学逻辑的辅助组件被停用以节省电力，直到接收到等待的外部事件响应。

8. 发明授权

US07043579B2 Ring-topology based multiprocessor data access bus 失效
标题翻译：基于环形拓扑的多处理器数据访问总线
公开(公告)号：US07043579B2
公开(公告)日：2006-05-09
申请号：US10313741
申请日：2002-12-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , John Samuel Liberty , Peichun Peter Liu
发明人： Sang Hoo Dhong , Harm Peter Hofstee , John Samuel Liberty , Peichun Peter Liu
IPC分类号： G06F13/00
CPC分类号： G06F13/4243
摘要： The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a data command ring, coupled to the plurality of APUs. The data command ring is employable to carry indicia of a selection of one of the plurality of APUs to the APUs. The data access ring also has a data address ring, coupled to the plurality of APUs. The data address ring is further employable to carry indicia of a memory location to the selected APU a predetermined number of clock cycles after the data command ring carries the indicia of the selection of one of the plurality of APUs. The data access ring also has a data transfer ring, coupled to the plurality of APUs. The data transfer ring is employable to transfer data to or from the memory location associated with the APU a predetermined number of clock cycles after the data address ring carries the indicia of the memory location to the selected APU.
摘要翻译：本发明提供一种数据访问环。数据访问环具有多个附接的处理器单元（APU）和与每个APU相关联的本地存储器。数据访问环具有耦合到多个APU的数据命令环。数据命令环可用于将多个APU中的一个APU的选择的标记携带到APU。数据访问环还具有耦合到多个APU的数据地址环。数据地址环还可用于在数据命令环携带多个APU中的一个APU的选择的标记之后，将所选择的APU的存储位置的标记携带预定数量的时钟周期。数据访问环还具有耦合到多个APU的数据传送环。在数据地址环将存储器位置的标记传送到所选择的APU之后，数据传送环可用于将数据传送到与APU相关联的存储器位置的数据到预定数量的时钟周期。

9. 发明授权

US07986330B2 Method and apparatus for generating gammacorrected antialiased lines 有权
标题翻译：用于产生伽马校正抗锯齿线的方法和装置
公开(公告)号：US07986330B2
公开(公告)日：2011-07-26
申请号：US09833348
申请日：2001-04-12
申请人： Daniel Alan Brokenshire , Bruce David D'Amora , Gordon Clyde Fossum , Charles Ray Johns , John Samuel Liberty , Brad William Michael
发明人： Daniel Alan Brokenshire , Bruce David D'Amora , Gordon Clyde Fossum , Charles Ray Johns , John Samuel Liberty , Brad William Michael
IPC分类号： G09G5/00
CPC分类号： G09G5/393 , G06T11/203 , G06T2200/12 , G09G2320/0276 , G09G2340/10
摘要： A method, apparatus, and computer implemented instructions for generating antialiased lines for display in a data processing system. Graphics data is received for display, wherein the graphics data includes primitives defining lines. A gamma correction is applied to the graphics data on a per primitive basis to form antialiased lines. The antialiased lines are displayed.
摘要翻译：一种用于生成用于在数据处理系统中显示的抗锯齿线的方法，装置和计算机实现的指令。接收用于显示的图形数据，其中图形数据包括定义线的图元。基于每个原始图像数据应用伽马校正以形成抗锯齿线。显示抗锯齿线。

10. 发明授权

US06421053B1 Block rendering method for a graphics subsystem 有权
标题翻译：图形子系统的块渲染方法
公开(公告)号：US06421053B1
公开(公告)日：2002-07-16
申请号：US09316097
申请日：1999-05-24
申请人： Charles Ray Johns , John Samuel Liberty , Brad William Michael , John Fred Spannaus
发明人： Charles Ray Johns , John Samuel Liberty , Brad William Michael , John Fred Spannaus
IPC分类号： G06T1120
CPC分类号： G06T15/80
摘要： Primitives are divided into span groups of 2N spans, and then processed in M×N blocks of pixels, with the pixel blocks preferably being as close to square as possible and therefore optimized for small spans and texture mapping. Each span group is rendered block-by-block in a serpentine manner from an initial or entry block, first in a direction away from the long edge of the primitive and then in a direction towards the long edge. The interpolators include a one-deep stack onto which pixel and texel information for the initial or entry block are pushed before rendering any other blocks within the span group. Blocks or pairs of blocks within different span subgroups of the span group are then alternately rendered, such that rendering zig-zags between the span subgroups as it proceeds to the end of the span group. Once the first end of a span group is reached, the values for the initial or entry block are popped from the stack and rendering resumes from the initial or entry block in the opposite direction, but in the same serpentine or zig-zag manner, until the other end of the span group is reached. The next span group, if any, is rendered starting with a block adjacent to the last block rendered in the previous span group. Memory bandwidth utilization between the pixel and texel cache and the frame buffer is thus improved, together with texel reuse during texture mapping, to reduce the total number of pixel and texel fetches required to render the primitive.
摘要翻译：原子被分成2N个跨度的跨度组，然后在M×N个像素块中进行处理，其中像素块优选尽可能接近正方形，因此针对小跨度和纹理映射进行优化。每个跨度组以蛇形方式从初始或进入块逐块渲染，首先在远离原始长边的方向上，然后朝向长边的方向。插值器包括一个深层堆叠，在渲染跨度组内的任何其他块之前，将初始或进入块的像素和纹素信息推送到其上。然后交替地渲染跨度组的不同跨度子组内的块或块对，使得当它进行到跨度组的末尾时，在跨越子组之间渲染之字形。一旦达到跨度组的第一个结束，初始或进入块的值从堆栈中弹出，并且渲染从初始或进入块以相反方向恢复，但是以相同的蛇形或锯齿形方式恢复，直到到达跨度组的另一端。下一个范围组（如果有的话）从与前一个范围组中呈现的最后一个块相邻的块开始绘制。因此，像素和纹素高速缓存和帧缓冲器之间的存储器带宽利用率在纹理映射期间与纹素复用一起得到改善，以减少呈现原始图像所需的像素和纹素提取的总数。

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