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    • 5. 发明授权
    • Method and apparatus for implementing balanced clock distribution networks on ASICs with voltage islands functioning at multiple operating points of voltage and temperature
    • 用于在电压岛在电压和温度的多个工作点处工作的ASIC上实现平衡时钟分配网络的方法和装置
    • US07551002B1
    • 2009-06-23
    • US12014172
    • 2008-01-15
    • Paul Gary ReulandBrian Andrew Schuelke
    • Paul Gary ReulandBrian Andrew Schuelke
    • H03K19/00
    • H03K5/1502G06F1/10
    • A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.
    • 一种在具有在电压和温度的多个工作点处工作的电压岛的专用集成电路(ASIC)上实现平衡时钟分配网络的方法和装置,以及提供主题电路所在的设计结构。 时钟源耦合到提供时钟信号的N电平平衡时钟树。 多个电压岛中的每一个包括相应的电压移位器和接收时钟信号的可编程延迟功能。 每个相应的电压移位器和可编程延迟功能为相关电压岛的相应的平衡时钟树提供第二时钟信号。 系统控制器为每个相应的电压移位器和可编程延迟功能提供相应的控制输入。 相应的控制输入根据各个电压岛的操作模式动态变化。
    • 6. 发明授权
    • Phase locked loop circuit having automatic range setting logic
    • 锁相环电路具有自动量程设定逻辑
    • US5764712A
    • 1998-06-09
    • US634504
    • 1996-04-18
    • Mark William BranstadPhilip Lynn LeichtyBrian Andrew Schuelke
    • Mark William BranstadPhilip Lynn LeichtyBrian Andrew Schuelke
    • H03L7/10H03L7/113
    • H03L7/10H03L7/113Y10S331/02
    • A method for setting a locking frequency operating range of the phase locked loop (PLL) circuit and a phase locked loop (PLL) circuit are provided with range select logic for detecting an unknown reference clock frequency and for setting a locking frequency operating range of the phase locked loop. First a bypass mode for the phase locked loop (PLL) circuit is set. An unknown reference clock frequency is applied to a first counter. A known oscillator clock frequency is applied to a second counter. The first and second counters are reset and a timeout value of the second counter is identified. A first counter count value is compared with precalculated constant values. A set of range bits are latched responsive to said compared values. Two consecutive sets of latched range bits are compared and the steps repeated until a match of two consecutive sets of latched range bits is identified. The matching latched range bits are applied to a programmable range select input of the phase locked loop (PLL) circuit.
    • 用于设置锁相环(PLL)电路和锁相环(PLL)电路的锁定频率工作范围的方法设置有用于检测未知参考时钟频率的范围选择逻辑,并且用于设置锁相环 锁相环。 首先设置锁相环(PLL)电路的旁路模式。 将未知的参考时钟频率应用于第一个计数器。 已知的振荡器时钟频率被施加到第二计数器。 第一和第二计数器被复位,并且识别出第二计数器的超时值。 将第一计数器计数值与预先计算的常数值进行比较。 响应于所述比较值而锁存一组范围位。 比较两个连续的锁存范围比特组,并重复步骤,直到两个连续的锁存范围比特组的匹配被识别。 匹配的锁存范围位被应用于锁相环(PLL)电路的可编程范围选择输入。
    • 7. 发明授权
    • Frequency shift detection circuit with selectable granularity
    • 具有可选粒度的频移检测电路
    • US6011412A
    • 2000-01-04
    • US70925
    • 1998-05-01
    • Jonathan William ByrnChad B. McBrideBrian Andrew Schuelke
    • Jonathan William ByrnChad B. McBrideBrian Andrew Schuelke
    • H03D13/00
    • H03D13/004
    • A frequency shift detection circuit for detecting a frequency shift between a first signal and a second signal includes two or more delay circuits coupled to one another in series and two or more comparison logic circuits. The first delay circuit in the series receives one of the first and second signals and produces a delayed replica. Each of the other delay circuits receives the delayed replica produced by the previous delay circuit in the series and produces a further delayed replica. Thus, the signal produced by each delay circuit is delayed from the original signal by a different amount. Each comparison logic circuit receives one of the delayed replicas and receives the other one of the first and second signals, i.e., the one that is not received by the delay circuits. In response, the comparison logic circuit produces a frequency shift detection signal when it detects a phase difference between that other one of said first and second signals and the delayed replica. By selecting or tapping one of the outputs of the comparison logic circuits, a user can select the detection granularity.
    • 用于检测第一信号和第二信号之间的频移的频移检测电路包括串联耦合的两个或更多个延迟电路和两个或更多个比较逻辑电路。 该系列中的第一个延迟电路接收第一和第二信号中的一个并产生延迟的副本。 每个其他延迟电路接收由串联中的先前延迟电路产生的延迟复制品,并产生另一延迟复制品。 因此,由每个延迟电路产生的信号从原始信号延迟不同的量。 每个比较逻辑电路接收一个延迟的副本并且接收第一和第二信号中的另一个,即未被延迟电路接收的信号。 作为响应,当比较逻辑电路检测到所述第一和第二信号中的另一个与延迟的副本之间的相位差时,产生频移检测信号。 通过选择或敲击比较逻辑电路的输出之一,用户可以选择检测粒度。