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1. 发明授权

US09098435B1 Finite impulse response filter with parallel input 有权
标题翻译：具有并行输入的有限脉冲响应滤波器
公开(公告)号：US09098435B1
公开(公告)日：2015-08-04
申请号：US11540142
申请日：2006-09-28
申请人： David S. Nelson , Scott Talbot , Ryan Hinton , Osama Haddadin
发明人： David S. Nelson , Scott Talbot , Ryan Hinton , Osama Haddadin
IPC分类号： G06F17/14 , G06F7/53
CPC分类号： G06F17/14 , G06F7/53 , H03H17/045 , H03H17/06 , H03H2218/06
摘要： A filter and method for finite impulse response filtering an input signal is described. In one embodiment, the filter includes an input circuit configured to receive input samples in parallel, where the parallel input samples correspond to sequential samples of the input signal. In another embodiment, the filter includes a coefficient memory configured to store filter response coefficients and output a subset of those coefficients corresponding to a selected decimation factor.
摘要翻译：描述了一种用于对输入信号进行有限脉冲响应滤波的滤波器和方法。在一个实施例中，滤波器包括被配置为并行地接收输入采样的输入电路，其中并行输入样本对应于输入信号的顺序采样。在另一个实施例中，滤波器包括被配置为存储滤波器响应系数并输出对应于所选抽取因子的那些系数的子集的系数存储器。

2. 发明授权

US06954622B2 Cooperative transmission power control method and system for CDMA communication systems 有权
标题翻译： CDMA通信系统协同传输功率控制方法及系统
公开(公告)号：US06954622B2
公开(公告)日：2005-10-11
申请号：US10059938
申请日：2002-01-29
申请人： David S. Nelson , Lyman D. Horne , Delon K. Jones
发明人： David S. Nelson , Lyman D. Horne , Delon K. Jones
IPC分类号： H04B7/005 , H01Q11/12
CPC分类号： H04W52/228 , H04W52/146 , H04W52/226 , H04W52/54
摘要： A method and system for cooperative transmission power control in a communication system is provided. The method, operating within a system having a base station and at least on mobile station, includes the step of providing a power control data structure having memory fields indexed according to a predetermined parameter set. The next step retrieves from one of the memory fields a transmission power control value and adjusts a transmission power level of the mobile station according to the retrieved value.
摘要翻译：提供了一种用于通信系统中协同传输功率控制的方法和系统。该方法在具有基站并且至少在移动台上的系统内工作，包括提供具有根据预定参数集索引的存储器字段的功率控制数据结构的步骤。下一步骤从一个存储器区域检索传输功率控制值，并根据检索的值调整移动站的发射功率电平。

3. 发明授权

US5173337A Construction process for simulating a desirable appearance 失效
标题翻译：模拟理想外观的施工过程
公开(公告)号：US5173337A
公开(公告)日：1992-12-22
申请号：US660528
申请日：1991-02-25
申请人： David S. Nelson
发明人： David S. Nelson
IPC分类号： B44F9/04 , E04F13/14 , E04F21/16
CPC分类号： E04F13/147 , B44F9/04 , E04F21/1655
摘要： A construction process and product thereof are provided which include affixing a construction medium simulating the appearance of solid stone to a construction frame to simulate a desirable appearance.
摘要翻译：提供了一种构造方法及其制造方法，其包括将模拟实心石的外观的构造介质固定在构造框架上以模拟期望的外观。

4. 发明授权

US07697641B2 Parallel DSP demodulation for wideband software-defined radios 有权
标题翻译：用于宽带软件定义无线电的并行DSP解调
公开(公告)号：US07697641B2
公开(公告)日：2010-04-13
申请号：US10878902
申请日：2004-06-28
申请人： Osama Sami Haddadin , Brad Terry Hansen , David S. Nelson , Roland Richard Henrie
发明人： Osama Sami Haddadin , Brad Terry Hansen , David S. Nelson , Roland Richard Henrie
IPC分类号： H04L27/06
CPC分类号： H04B1/0092 , H04B1/0003 , H04B1/28 , H04L7/0029 , H04L7/0332
摘要： A demodulator, suitable for use in a communication system and in a modem, has a block polyphase circuit with circuit blocks for different signal processing functions, particularly filtering, delay, and frequency conversion. The circuit blocks are arranged for parallel processing of different portions of an input sequence of signals. Signals of the input sequence to be filtered are divided among the blocks by a demultiplexer for processing at a clock frequency lower than a clock frequency of the input signal sequence. Signals outputted by groups of the circuit blocks are summed to produce an output signal of the group. Output signals of all of the groups are multiplexed to provide an output signal sequence such that the repetition frequency of the outputted signals may be higher, lower, or equal to that of the input signal sequence. This enables use of programmable circuitry operative at reduced clock rates.
摘要翻译：适用于通信系统和调制解调器的解调器具有块多相电路，具有用于不同信号处理功能的电路块，特别是滤波，延迟和频率转换。电路块被布置用于对输入信号序列的不同部分进行并行处理。要被滤波的输入序列的信号由解复用器在块之间划分，以在低于输入信号序列的时钟频率的时钟频率处理。将由电路块的组输出的信号相加以产生该组的输出信号。所有组的输出信号被复用以提供输出信号序列，使得输出信号的重复频率可以高于，低于或等于输入信号序列的重复频率。这使得可以使用以降低的时钟速率工作的可编程电路。

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