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1. 发明申请

US20100293312A1 Network Communications Processor Architecture 有权
标题翻译：网络通信处理器架构
公开(公告)号：US20100293312A1
公开(公告)日：2010-11-18
申请号：US12782379
申请日：2010-05-18
申请人： David P. Sonnier , William G. Burroughs , Narender R. Vangati , Deepak Mital , Robert J. Munoz
发明人： David P. Sonnier , William G. Burroughs , Narender R. Vangati , Deepak Mital , Robert J. Munoz
IPC分类号： G06F15/76 , G06F13/36 , G06F12/08 , G06F9/02
CPC分类号： G06F15/167 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.
摘要翻译：描述的实施例提供一种具有多个处理器核心和与核心直接通信的公共存储器的系统。源处理核心通过为任务目标核心生成任务消息与任务目标核心通信。任务源核心将任务消息直接发送到与任务源核心相邻的接收处理核心。如果接收处理核心不是任务目标核心，则接收处理核心将任务消息不改变地传递到与接收处理核心相邻的处理核心。如果接收处理核心是任务目标核心，则任务目标核心处理消息。

2. 发明授权

US09081742B2 Network communications processor architecture 有权
标题翻译：网络通讯处理器架构
公开(公告)号：US09081742B2
公开(公告)日：2015-07-14
申请号：US12782379
申请日：2010-05-18
申请人： David P. Sonnier , William G. Burroughs , Narender R. Vangati , Deepak Mital , Robert J. Munoz
发明人： David P. Sonnier , William G. Burroughs , Narender R. Vangati , Deepak Mital , Robert J. Munoz
IPC分类号： G06F15/167 , H04L12/933 , H04L12/931
CPC分类号： G06F15/167 , H04L49/101 , H04L49/109 , H04L49/506
摘要： Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.
摘要翻译：描述的实施例提供一种具有多个处理器核心和与核心直接通信的公共存储器的系统。源处理核心通过为任务目标核心生成任务消息与任务目标核心通信。任务源核心将任务消息直接发送到与任务源核心相邻的接收处理核心。如果接收处理核心不是任务目标核心，则接收处理核心将任务消息不改变地传递到与接收处理核心相邻的处理核心。如果接收处理核心是任务目标核心，则任务目标核心处理消息。

3. 发明授权

US06691190B1 Inter-DSP data exchange in a multiple DSP environment 有权
标题翻译： DSP数据交换在多DSP环境中
公开(公告)号：US06691190B1
公开(公告)日：2004-02-10
申请号：US09490434
申请日：2000-01-24
申请人： William G. Burroughs , Steven J. Pollock
发明人： William G. Burroughs , Steven J. Pollock
IPC分类号： G06F1300
CPC分类号： G06F15/16 , G06F9/546
摘要： An inter-processor data exchange system is provided in a multiple processor environment. The system includes a first message unit and a second message unit. The first message unit stores first data from a first processor and transfers the stored first data to the second message unit. The second message unit stores the first data from the first message unit and responsively provides the first data to a second processor. The second message unit also stores second data from the second processor and transfers the stored second data to the first message unit, and the first message unit stores the second data from the second message unit and responsively provides the second data to the first processor. Each message unit also provides an interrupt signal to the other processor for informing the other processor that the data is available for reading. In addition, each message unit provides a first flag signal for informing its own processor that the other processor has read the data.
摘要翻译：在多处理器环境中提供了一个处理器间数据交换系统。该系统包括第一消息单元和第二消息单元。第一消息单元存储来自第一处理器的第一数据，并将存储的第一数据传送到第二消息单元。第二消息单元存储来自第一消息单元的第一数据，并且响应地将第一数据提供给第二处理器。第二消息单元还存储来自第二处理器的第二数据并将存储的第二数据传送到第一消息单元，并且第一消息单元存储来自第二消息单元的第二数据，并且响应地将第二数据提供给第一处理器。每个消息单元还向另一个处理器提供中断信号，以通知其他处理器该数据可用于读取。此外，每个消息单元提供第一标志信号，用于通知其自己的处理器其他处理器已经读取数据。

4. 发明授权

US06535948B1 Serial interface unit 有权
标题翻译：串行接口单元
公开(公告)号：US06535948B1
公开(公告)日：2003-03-18
申请号：US09583493
申请日：2000-05-31
申请人： Paul Kurt Wheeler , Andrew Lawrence Webb , William G. Burroughs
发明人： Paul Kurt Wheeler , Andrew Lawrence Webb , William G. Burroughs
IPC分类号： G06F1336
CPC分类号： G06F13/14
摘要： A serial interface unit having an input shift register adapted to receive a serial input data from a serial data stream, and a destination request module. The input shift register converting the serial input data into a parallel input data. The input shift register in communication with at least two processors and the destination request module. The destination request module in communication with one of the at least two processors in response to an input shift register status signal and a processor designation signal, the selected processor adapted to receive the parallel input data.
摘要翻译：具有适于从串行数据流接收串行输入数据的输入移位寄存器的串行接口单元和目的地请求模块。输入移位寄存器将串行输入数据转换为并行输入数据。与至少两个处理器和目的地请求模块通信的输入移位寄存器。所述目的地请求模块响应于输入移位寄存器状态信号和处理器指定信号而与所述至少两个处理器之一通信，所述处理器适于接收并行输入数据。

5. 发明授权

US6076136A RAM address decoding system and method to support misaligned memory access 失效
标题翻译： RAM地址解码系统和支持不对齐内存访问的方法
公开(公告)号：US6076136A
公开(公告)日：2000-06-13
申请号：US99885
申请日：1998-06-17
申请人： William G. Burroughs , Charles Raymond Miller
发明人： William G. Burroughs , Charles Raymond Miller
IPC分类号： G06F12/04 , G06F12/06 , G11C8/00 , G11C8/10 , G06F12/00
CPC分类号： G11C8/00 , G06F12/04 , G11C8/10 , G06F12/0607
摘要： A memory access system is provided for accessing a first data unit and a second data unit in a single memory access cycle. The memory access system provides at least a memory, an even address decoding circuit, an odd address decoder, and shift logic. The memory is interleaved by at least one address bus signal into an even memory bank and an odd memory bank. The even memory bank and the odd memory bank are each organized by a plurality of corresponding rows. Each one of the rows contains at least one storage location for a data unit, with one address mapped to one storage location. The even address decoding circuit decodes an address bus signal supplied to the input terminal and activates an output terminal coupled to enable the given row of the even memory bank. The odd address decoder decodes the address bus signal to activate an output terminal coupled to enable the row of the odd memory bank in which the first data unit resides. The shift logic processes input signals indicating a mis-aligned access of multiple data units to produce a shift signal, and the even address decoding circuit is responsive to the shift signal to increment or shift the output terminal activated by decoding the address bus signal. The first data unit is made accessible by enabling the given row of the odd memory bank, and the second data unit is made accessible by enabling the next sequential row of the even memory bank.
摘要翻译：提供存储器访问系统，用于在单个存储器访问周期中访问第一数据单元和第二数据单元。存储器访问系统至少提供存储器，偶数地址解码电路，奇数地址译码器和移位逻辑。该存储器由至少一个地址总线信号交织到偶数存储体和奇数存储体中。偶数存储体和奇数存储体都由多个对应的行组织。行中的每一行至少包含一个数据单元的存储位置，一个地址映射到一个存储位置。偶数地址解码电路对提供给输入端的地址总线信号进行解码，并激活耦合以使得偶数存储体的给定行的输出端。奇地址解码器解码地址总线信号以激活耦合的输出端子，以使第一数据单元所在的奇数存储器组的行能够实现。移位逻辑处理指示多个数据单元的错误对准访问以产生移位信号的输入信号，并且偶数地址解码电路响应于移位信号来增加或移位通过解码地址总线信号而被激活的输出端。通过启用奇数存储体的给定行可以使第一数据单元可访问，并且通过启用偶数存储体的下一个顺序行使第二数据单元可访问。

6. 发明授权

US5517147A Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits 失效
标题翻译：用于集成电路的多相时钟信号发生器，包括PLL，计数器和逻辑电路
公开(公告)号：US5517147A
公开(公告)日：1996-05-14
申请号：US341523
申请日：1994-11-17
申请人： William G. Burroughs , Andrew Neely , Joseph A. Manzella
发明人： William G. Burroughs , Andrew Neely , Joseph A. Manzella
IPC分类号： G06F1/06 , H03K5/15 , H03L7/06 , H03K3/00
CPC分类号： G06F1/06 , H03K5/1506 , H03L7/06
摘要： A multiple-phase clock signal generator includes a phase-locked loop (PLL) for generating an oscillating signal having a predetermined frequency, a counter driven by the oscillating signal and having a plurality of outputs, and a plurality of combinational logic gates each having a plurality of inputs and an output. Selected ones of the inputs of each combinational logic gate are coupled to selected outputs of the counter to produce, at the output of each combinational logic gate, a clock signal having a particular phase. Different combinations of the outputs of the counter can be used to generate different phases.
摘要翻译：多相时钟信号发生器包括用于产生具有预定频率的振荡信号的锁相环（PLL），由振荡信号驱动并具有多个输出的计数器以及多个组合逻辑门，每个具有一个多个输入和输出。每个组合逻辑门的选择的输入被耦合到计数器的选定输出，以在每个组合逻辑门的输出处产生具有特定相位的时钟信号。可以使用计数器的输出的不同组合来产生不同的相位。

7. 发明授权

US5133124A Method for compacting recyclable plastic containers 失效
标题翻译：压缩可回收塑料容器的方法
公开(公告)号：US5133124A
公开(公告)日：1992-07-28
申请号：US596855
申请日：1990-10-12
申请人： William G. Burroughs
发明人： William G. Burroughs
IPC分类号： B26F1/24 , B29B17/00 , B30B9/32
CPC分类号： B30B15/08 , B26F1/24 , B29B17/0052 , B30B9/325 , B26F2210/11 , B29B2017/0057 , Y02W30/62 , Y10S100/902 , Y10S264/918 , Y10T29/49751 , Y10T29/4987 , Y10T29/49936
摘要： A method for permanently compacting a hollow resilient structure such as a recyclable plastic container to facilitate recycling thereof. As the structure is compressed cutting blades provided on the compressing surface perforate the walls of the container thereby cutting interlocking tabs into the surface. At the same time the interlocking tabs are forced outward and through the cavity left in the walls of the container by displacement of the tabs. The tabs straddle the cavity and become locked against the walls of the container by the separating force of the resilient plastic.
摘要翻译：用于永久地压缩诸如可回收塑料容器之类的空心弹性结构以便于回收的方法。由于结构是设置在压缩表面上的压缩的切割刀片穿过容器的壁，从而将互锁突片切割到表面中。同时，通过突片的移位，互锁突片被迫向外并且通过留在容器的壁中的空腔。突片跨过空腔并通过弹性塑料的分离力而被锁定在容器的壁上。

8. 发明授权

US07389368B1 Inter-DSP signaling in a multiple DSP environment 失效
标题翻译：多DSP环境中的DSP信号
公开(公告)号：US07389368B1
公开(公告)日：2008-06-17
申请号：US09489652
申请日：2000-01-24
申请人： William G. Burroughs , Steven J. Pollock
发明人： William G. Burroughs , Steven J. Pollock
IPC分类号： G06F3/00 , G06F13/24
CPC分类号： G06F13/24
摘要： The invention includes a method and apparatus for synchronizing a first processor with a second processor. The method includes storing in a register parallel bits of data from the first processor, wherein at least one bit of data is a logic ONE. An output signal is formed from the one bit of data in the register. The output signal is sent as an interrupt signal to an interrupt terminal of the second processor for synchronizing the first processor with the second processor. The method may be used with a memory mapped register or an off-core register. The first and second processors may each be a digital signal processor (DSP) or any other type of processor.
摘要翻译：本发明包括一种用于使第一处理器与第二处理器同步的方法和装置。该方法包括在寄存器中并行存储来自第一处理器的数据位，其中数据的至少一位是逻辑1。输出信号由寄存器中的一位数据形成。输出信号作为中断信号发送到第二处理器的中断端，用于使第一处理器与第二处理器同步。该方法可以与存储器映射寄存器或非核心寄存器一起使用。第一和第二处理器可以各自为数字信号处理器（DSP）或任何其他类型的处理器。

9. 发明授权

US4773041A System for executing a sequence of operation codes with some codes being executed out of order in a pipeline parallel processor 失效
标题翻译：用于执行一系列操作代码的系统，其中一些代码在流水线并行处理器中是无序执行的
公开(公告)号：US4773041A
公开(公告)日：1988-09-20
申请号：US869349
申请日：1986-06-02
申请人： Joseph A. Hassler , William G. Burroughs
发明人： Joseph A. Hassler , William G. Burroughs
IPC分类号： G06F9/38 , G06F13/16 , G06F9/00
CPC分类号： G06F13/1642 , G06F9/3824 , G06F9/3834 , G06F9/3836
摘要： A referencing unit which creates addresses for main memory. Specifically, this reference unit is pipelined in the manner in which it receives the operators to be executed. Concurrency is achieved by allowing any number of read-type operations to be started before operators that are waiting for a store operation to finish even though these latter operators may appear earlier in the code stream. There are two inputs into the reference unit. Each is provided with a queue, one for receiving operators and address couples and another for receiving the output from the top-of-the-stack mechanism residing in the processor. The former is called an address coupled queue and the latter is called a top-of-stack queue. Since the address couple queue operators require no stack inputs, they enter the reference pipeline, two pipeline levels below where the top-of-stack operators enter the pipeline. This out-of-order execution allows the pipeline to remain full (with address couple queue operators) even though the top-of-stack operator is waiting for an input to become available.
摘要翻译：为主存储器创建地址的引用单元。特别地，该参考单元以其接收要执行的操作符的方式流水线化。通过允许在等待存储操作的操作员完成即使后面的操作符可能在代码流中更早出现的任何数量的读取类型操作来实现并发。参考单元有两个输入。每个都有一个队列，一个用于接收操作员和地址对，另一个用于接收位于处理器中的堆栈顶部机制的输出。前者称为地址耦合队列，后者称为堆栈顶部队列。由于地址对偶队列运算符不需要堆栈输入，所以它们进入参考流水线，两个流水线级别在堆栈顶层操作符进入管道之下。即使堆栈顶层操作符等待输入可用，这种无序执行允许管道保持完整（具有地址对偶队列操作符）。

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