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1. 发明授权

US08286238B2 Method and apparatus for run-time in-memory patching of code from a service processor 有权
标题翻译：从服务处理器的代码运行时内存补丁的方法和装置
公开(公告)号：US08286238B2
公开(公告)日：2012-10-09
申请号：US11540373
申请日：2006-09-29
申请人： David M. Durham , Hormuzd M. Khosravi , Travis Schluessler , Ravi Sahita , Uday R. Savagaonkar
发明人： David M. Durham , Hormuzd M. Khosravi , Travis Schluessler , Ravi Sahita , Uday R. Savagaonkar
IPC分类号： H04L29/06
CPC分类号： G06F8/656
摘要： Methods and apparatuses enable in-memory patching of a program loaded in volatile memory. A service processor identifies a program to be patched and an associated patch for the program. The patch is loaded into memory, including applying relocation fix-ups to the patch. The service processor directs the program to the patch in place of the segment of the program to be patched. The program implements the patch while maintaining program state, and without suspending execution of the program.
摘要翻译：方法和装置使得能够在加载在易失性存储器中的程序的内存中修补。服务处理器识别要修补的程序和程序的相关修补程序。修补程序加载到内存中，包括将修补程序应用于修补程序。服务处理器将程序引导到补丁代替要修补的程序的段。该程序在维护程序状态的同时实现补丁，并且不会暂停程序的执行。

2. 发明申请

US20080083030A1 Method and apparatus for run-time in-memory patching of code from a service processor 有权
标题翻译：从服务处理器的代码运行时内存补丁的方法和装置
公开(公告)号：US20080083030A1
公开(公告)日：2008-04-03
申请号：US11540373
申请日：2006-09-29
申请人： David M. Durham , Hormuzd M. Khosravi , Travis Schluessler , Ravi Sahita , Uday R. Savagaonkar
发明人： David M. Durham , Hormuzd M. Khosravi , Travis Schluessler , Ravi Sahita , Uday R. Savagaonkar
IPC分类号： G06F12/14
CPC分类号： G06F8/656
摘要： Methods and apparatuses enable in-memory patching of a program loaded in volatile memory. A service processor identifies a program to be patched and an associated patch for the program. The patch is loaded into memory, including applying relocation fix-ups to the patch. The service processor directs the program to the patch in place of the segment of the program to be patched. The program implements the patch while maintaining program state, and without suspending execution of the program.
摘要翻译：方法和装置使得能够在加载在易失性存储器中的程序的内存中修补。服务处理器识别要修补的程序和程序的相关修补程序。修补程序加载到内存中，包括将修补程序应用于修补程序。服务处理器将程序引导到补丁代替要修补的程序的段。该程序在维护程序状态的同时实现补丁，并且不会暂停程序的执行。

3. 发明申请

US20100262739A1 IDENTIFIER ASSOCIATED WITH MEMORY LOCATIONS FOR MANAGING MEMORY ACCESSES 有权
标题翻译：与记忆管理存储器相关联的标识符
公开(公告)号：US20100262739A1
公开(公告)日：2010-10-14
申请号：US12824074
申请日：2010-06-25
申请人： David Durham , Ravi Sahita , Uday R. Savagaonkar , Priya Rajagopal , Hormuzd M. Khosravi
发明人： David Durham , Ravi Sahita , Uday R. Savagaonkar , Priya Rajagopal , Hormuzd M. Khosravi
IPC分类号： G06F12/00 , G06F13/24
CPC分类号： G06F12/1491
摘要： Embodiments of apparatuses, articles, methods, and systems for associating identifiers with memory locations for controlling memory accesses are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述用于将标识符与用于控制存储器访问的存储器位置相关联的装置，物品，方法和系统的实施例。可以描述和要求保护其他实施例。

4. 发明授权

US07761674B2 Identifier associated with memory locations for managing memory accesses 有权
标题翻译：与用于管理内存访问的内存位置相关联的标识符
公开(公告)号：US07761674B2
公开(公告)日：2010-07-20
申请号：US11322669
申请日：2005-12-30
申请人： David Durham , Ravi Sahita , Uday R. Savagaonkar , Priya Rajagopal , Hormuzd M. Khosravi
发明人： David Durham , Ravi Sahita , Uday R. Savagaonkar , Priya Rajagopal , Hormuzd M. Khosravi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1491
摘要： Embodiments of apparatuses, articles, methods, and systems for associating identifiers with memory locations for controlling memory accesses are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述用于将标识符与用于控制存储器访问的存储器位置相关联的装置，物品，方法和系统的实施例。可以描述和要求保护其他实施例。

5. 发明授权

US07865683B2 Identifier associated with memory locations for managing memory accesses 有权
标题翻译：与用于管理内存访问的内存位置相关联的标识符
公开(公告)号：US07865683B2
公开(公告)日：2011-01-04
申请号：US12824074
申请日：2010-06-25
申请人： David Durham , Ravi Sahita , Uday R. Savagaonkar , Priya Rajagopal , Hormuzd M. Khosravi
发明人： David Durham , Ravi Sahita , Uday R. Savagaonkar , Priya Rajagopal , Hormuzd M. Khosravi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1491
摘要： Embodiments of apparatuses, articles, methods, and systems for associating identifiers with memory locations for controlling memory accesses are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述用于将标识符与用于控制存储器访问的存储器位置相关联的装置，物品，方法和系统的实施例。可以描述和要求保护其他实施例。

6. 发明申请

US20080134321A1 Tamper-resistant method and apparatus for verification and measurement of host agent dynamic data updates 审中-公开
标题翻译：用于验证和测量主机代理动态数据更新的防篡改方法和装置
公开(公告)号：US20080134321A1
公开(公告)日：2008-06-05
申请号：US11648252
申请日：2006-12-29
申请人： Priya Rajagopal , Travis Schluessler , Uday R. Savagaonkar , David Durham , Ravi Sahita , Uri Blumenthal
发明人： Priya Rajagopal , Travis Schluessler , Uday R. Savagaonkar , David Durham , Ravi Sahita , Uri Blumenthal
IPC分类号： H04L9/32
CPC分类号： G06F21/55 , G06F21/52 , G06F21/6281 , G06F21/64 , H04L9/3242 , H04L9/3247 , H04L63/06 , H04L63/123 , H04L63/1441
摘要： A platform for verifying the validity of changes to dynamic data modifiable during the runtime execution of an agent. In one embodiment, a management mode of a processor uses key information to generate a signature for a set of dynamic data, the signature to verify the validity of the state of the dynamic data to an integrity measurement agent.
摘要翻译：用于验证代理程序运行时执行期间可修改动态数据的更改的有效性的平台。在一个实施例中，处理器的管理模式使用密钥信息来生成一组动态数据的签名，该签名用于向完整性测量代理验证动态数据的状态的有效性。

7. 发明申请

US20090172341A1 USING A MEMORY ADDRESS TRANSLATION STRUCTURE TO MANAGE PROTECTED MICRO-CONTEXTS 有权
标题翻译：使用存储器地址转换结构来管理保护的MICR-CONTEXTS
公开(公告)号：US20090172341A1
公开(公告)日：2009-07-02
申请号：US11967458
申请日：2007-12-31
申请人： David M. Durham , Uday R. Savagaonkar , Ravi Sahita
发明人： David M. Durham , Uday R. Savagaonkar , Ravi Sahita
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F9/461 , G06F12/1036 , G06F12/109 , G06F12/145 , G06F2212/651
摘要： Embodiments of an invention for using a memory address translation structure to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, and determination logic. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address. The determination logic is to determine whether an entry is storing an address of a different data structure for the first translation stage.
摘要翻译：公开了使用存储器地址转换结构来管理受保护的微上下文的发明的实施例。在一个实施例中，一种装置包括接口和存储器管理逻辑。该接口是执行一个事务来从内存中获取信息。存储器管理逻辑将非翻译地址转换为存储器地址。存储器管理逻辑包括存储位置，一系列转换级和确定逻辑。存储位置是存储用于第一翻译阶段的数据结构的地址。每个翻译阶段包括翻译逻辑，以基于未翻译地址的一部分在数据结构中找到条目。每个条目是存储用于第一翻译阶段的不同数据结构的地址，用于连续翻译阶段的数据结构的地址或物理地址。确定逻辑是确定条目是否存储用于第一翻译阶段的不同数据结构的地址。

8. 发明授权

US08560806B2 Using a multiple stage memory address translation structure to manage protected micro-contexts 有权
标题翻译：使用多级存储器地址转换结构来管理受保护的微环境
公开(公告)号：US08560806B2
公开(公告)日：2013-10-15
申请号：US11967458
申请日：2007-12-31
申请人： David M. Durham , Uday R. Savagaonkar , Ravi Sahita
发明人： David M. Durham , Uday R. Savagaonkar , Ravi Sahita
IPC分类号： G06F12/10 , G06F9/46
CPC分类号： G06F12/1009 , G06F9/461 , G06F12/1036 , G06F12/109 , G06F12/145 , G06F2212/651
摘要： Embodiments of an invention for using a memory address translation structure to manage protected micro-contexts are disclosed. In one embodiment, an apparatus includes an interface and memory management logic. The interface is to perform a transaction to fetch information from a memory. The memory management logic is to translate an untranslated address to a memory address. The memory management logic includes a storage location, a series of translation stages, and determination logic. The storage location is to store an address of a data structure for the first translation stage. Each of the translation stages includes translation logic to find an entry in a data structure based on a portion of the untranslated address. Each entry is to store an address of a different data structure for the first translation stage, an address of a data structure for a successive translation stage, or the physical address. The determination logic is to determine whether an entry is storing an address of a different data structure for the first translation stage.
摘要翻译：公开了使用存储器地址转换结构来管理受保护的微上下文的发明的实施例。在一个实施例中，一种装置包括接口和存储器管理逻辑。该接口是执行一个事务来从内存中获取信息。存储器管理逻辑将非翻译地址转换为存储器地址。存储器管理逻辑包括存储位置，一系列转换级和确定逻辑。存储位置是存储用于第一翻译阶段的数据结构的地址。每个翻译阶段包括翻译逻辑，以基于未翻译地址的一部分在数据结构中找到条目。每个条目是存储用于第一翻译阶段的不同数据结构的地址，用于连续翻译阶段的数据结构的地址或物理地址。确定逻辑是确定条目是否存储用于第一翻译阶段的不同数据结构的地址。

9. 发明申请

US20090172346A1 TRANSITIONING BETWEEN SOFTWARE COMPONENT PARTITIONS USING A PAGE TABLE POINTER TARGET LIST 审中-公开
标题翻译：软件组件分段之间的转换使用一个页表指针目标列表
公开(公告)号：US20090172346A1
公开(公告)日：2009-07-02
申请号：US11967500
申请日：2007-12-31
申请人： Ravi Sahita , Uday R. Savagaonkar , David M. Durham , Andrew V. Anderson , Ulhas Warrier
发明人： Ravi Sahita , Uday R. Savagaonkar , David M. Durham , Andrew V. Anderson , Ulhas Warrier
IPC分类号： G06F9/26
CPC分类号： G06F12/145 , G06F9/5077
摘要： Embodiments of apparatuses, articles, methods, and systems for intra-partitioning components within an execution environment, and transitioning between partitions using a page table pointer target list are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里一般地描述使用页表指针目标列表在执行环境内进行分区内组件的设备，物品，方法和系统的实施例以及在分区之间的转换。可以描述和要求保护其他实施例。

10. 发明授权

US08799673B2 Seamlessly encrypting memory regions to protect against hardware-based attacks 有权
标题翻译：无缝加密内存区域以防止基于硬件的攻击
公开(公告)号：US08799673B2
公开(公告)日：2014-08-05
申请号：US12651432
申请日：2009-12-31
申请人： Uday R. Savagaonkar , Ravi Sahita , David Durham , Men Long
发明人： Uday R. Savagaonkar , Ravi Sahita , David Durham , Men Long
IPC分类号： H04L29/06
CPC分类号： G06F12/1408 , G06F12/1441 , G06F2212/1052
摘要： Systems, apparatuses, and methods, and for seamlessly protecting memory regions to protect against hardware-based attacks are disclosed. In one embodiment, an apparatus includes a decoder, control logic, and cryptographic logic. The decoder is to decode a transaction between a processor and memory-mapped input/output space. The control logic is to redirect the transaction from the memory-mapped input/output space to a system memory. The cryptographic logic is to operate on data for the transaction.
摘要翻译：公开了系统，装置和方法，并且用于无缝地保护存储器区域以防止基于硬件的攻击。在一个实施例中，一种装置包括解码器，控制逻辑和加密逻辑。解码器是对处理器和存储器映射的输入/输出空间之间的事务进行解码。控制逻辑是将事务从内存映射的输入/输出空间重定向到系统内存。密码逻辑是对数据进行交易操作。

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