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1. 发明授权

US07363474B2 Method and apparatus for suspending execution of a thread until a specified memory access occurs 有权
标题翻译：用于挂起执行线程的方法和装置，直到发生指定的存储器访问
公开(公告)号：US07363474B2
公开(公告)日：2008-04-22
申请号：US10039579
申请日：2001-12-31
申请人： Dion Rodgers , Deborah T. Marr , David L. Hill , Shiv Kaushik , James B. Crossland , David A. Koufaty
发明人： Dion Rodgers , Deborah T. Marr , David L. Hill , Shiv Kaushik , James B. Crossland , David A. Koufaty
IPC分类号： G06F15/00 , G06F15/76 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3009 , G06F9/30079 , G06F9/3851 , G06F9/4812 , G06F9/4843
摘要： Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.
摘要翻译：暂停执行线程直到发生指定的内存访问的技术。在一个实施例中，处理器包括能够执行多个线程的多个执行单元。第一个线程包括指定监视器地址的指令。挂起逻辑挂起执行第一个线程，并且监视器导致第一个线程的恢复以响应对指定的监视器地址的访问。

2. 发明授权

US07127561B2 Coherency techniques for suspending execution of a thread until a specified memory access occurs 有权
公开(公告)号：US07127561B2
公开(公告)日：2006-10-24
申请号：US10039656
申请日：2001-12-31
申请人： David L. Hill , Deborah T. Marr , Dion Rodgers , Shiv Kaushik , James B. Crossland , David A. Koufaty
发明人： David L. Hill , Deborah T. Marr , Dion Rodgers , Shiv Kaushik , James B. Crossland , David A. Koufaty
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0831
摘要： Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having an operand indicating a monitor address and a bus controller. In one embodiment, the bus controller is to assert a preventative signal in response to receiving a memory access attempting to gain sufficient ownership of a cache line associated with said monitor address to allow modification of said cache line without generation of another transaction indicative of the modification. In another embodiment, the bus controller is to generate a bus cycle in response to the instruction to eliminate any ownership of the cache line by another processor that would allow a modification of the cache line without generation of another memory access indicative of the modification.

3. 发明授权

US06671795B1 Method and apparatus for pausing execution in a processor or the like 有权
标题翻译：用于在处理器等中暂停执行的方法和装置
公开(公告)号：US06671795B1
公开(公告)日：2003-12-30
申请号：US09489130
申请日：2000-01-21
申请人： Deborah T. Marr , Dion Rodgers
发明人： Deborah T. Marr , Dion Rodgers
IPC分类号： G06F948
CPC分类号： G06F9/3869 , G06F9/30083 , G06F9/30087 , G06F9/3009 , G06F9/3851 , G06F9/52
摘要： A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET instruction and a READ instruction. When a SET flag is retrieved for a given thread, the SET instruction sets a Bit flag in memory indicating that execution for the thread has been paused. The SET instruction is placed in the pipeline for execution. The following READ instruction for that thread, however, is prevented from entering the pipeline until, the SET instruction is executed and retired (resulting in a clearing of the Bit flag). Once the Bit flag has been cleared, the READ instruction is placed in the pipeline for execution. During the time that processing of one thread is paused, the execution of other threads may continue.
摘要翻译：描述用于暂停从线程执行指令的方法和装置。在一个实施例中，暂停指令被实现为两个指令或微指令：SET指令和READ指令。当为给定的线程检索SET标志时，SET指令在存储器中设置一个Bit标志，指示线程的执行已暂停。 SET指令放在流水线中执行。然而，针对该线程的以下READ指令被阻止进入流水线，直到SET指令被执行并退出（导致清除Bit标志）。一旦Bit标志被清除，READ指令被放置在流水线中才能执行。在一个线程的处理暂停的时间内，其他线程的执行可能会继续。

4. 发明授权

US07451296B2 Method and apparatus for pausing execution in a processor or the like 有权
标题翻译：用于在处理器等中暂停执行的方法和装置
公开(公告)号：US07451296B2
公开(公告)日：2008-11-11
申请号：US10728962
申请日：2003-12-08
申请人： Deborah T. Marr , Dion Rodgers
发明人： Deborah T. Marr , Dion Rodgers
IPC分类号： G06F7/38
CPC分类号： G06F9/3869 , G06F9/30083 , G06F9/30087 , G06F9/3009 , G06F9/3851 , G06F9/52
摘要： A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET instruction and a READ instruction. When a SET flag is retrieved for a given thread, the SET instruction sets a Bit flag in memory indicating that execution for the thread has been paused. The SET instruction is placed in the pipeline for execution. The following READ instruction for that thread, however, is prevented from entering the pipeline until, the SET instruction is executed and retired (resulting in a clearing of the Bit flag). Once the Bit flag has been cleared, the READ instruction is placed in the pipeline for execution. During the time that processing of one thread is paused, the execution of other threads may continue.
摘要翻译：描述用于暂停从线程执行指令的方法和装置。在一个实施例中，暂停指令被实现为两个指令或微指令：SET指令和READ指令。当为给定的线程检索SET标志时，SET指令在存储器中设置一个Bit标志，指示线程的执行已暂停。 SET指令放在流水线中执行。然而，针对该线程的以下READ指令被阻止进入流水线，直到SET指令被执行并退出（导致清除Bit标志）。一旦Bit标志被清除，READ指令被放置在流水线中才能执行。在一个线程的处理暂停的时间内，其他线程的执行可能会继续。

5. 发明授权

US06654837B1 Dynamic priority external transaction system 有权
标题翻译：动态优先级外部事务系统
公开(公告)号：US06654837B1
公开(公告)日：2003-11-25
申请号：US09474011
申请日：1999-12-28
申请人： David L. Hill , Derek T. Bachand , Chinna B. Prudvi , Deborah T. Marr
发明人： David L. Hill , Derek T. Bachand , Chinna B. Prudvi , Deborah T. Marr
IPC分类号： G06F1200
CPC分类号： G06F13/1642 , G06F13/18 , G06F13/362
摘要： A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.
摘要翻译：多模式事务队列可以根据默认优先级方案来操作。当检测到拥塞事件时，事务队列可以参与第二优先级方案。

6. 发明授权

US07143242B2 Dynamic priority external transaction system 有权
公开(公告)号：US07143242B2
公开(公告)日：2006-11-28
申请号：US10667457
申请日：2003-09-23
申请人： David L. Hill , Derek T. Bachand , Chinna B. Prudvi , Deborah T. Marr
发明人： David L. Hill , Derek T. Bachand , Chinna B. Prudvi , Deborah T. Marr
IPC分类号： G06F12/00
CPC分类号： G06F13/1642 , G06F13/18 , G06F13/362
摘要： A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.

7. 发明授权

US09081688B2 Obtaining data for redundant multithreading (RMT) execution 有权
标题翻译：获取冗余多线程（RMT）执行的数据
公开(公告)号：US09081688B2
公开(公告)日：2015-07-14
申请号：US12317801
申请日：2008-12-30
申请人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
发明人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/0817
摘要： In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于向第一高速缓存提供处于独占状态的高速缓存块的方法，并且当访问两个高速缓存的核心正在执行冗余线程时，以独占状态将相同的高速缓存块提供给第二高速缓存。描述和要求保护其他实施例。

8. 发明授权

US08793689B2 Redundant multithreading processor 有权
标题翻译：冗余多线程处理器
公开(公告)号：US08793689B2
公开(公告)日：2014-07-29
申请号：US12797361
申请日：2010-06-09
申请人： Glenn J. Hinton , Steven E. Raasch , Avinash Sodani , Sebastien Hily , John G. Holm , Ronak Singhal , Deborah T. Marr
发明人： Glenn J. Hinton , Steven E. Raasch , Avinash Sodani , Sebastien Hily , John G. Holm , Ronak Singhal , Deborah T. Marr
IPC分类号： G06F9/46 , G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/52 , G06F9/3851 , G06F11/1497 , G06F12/1027
摘要： A redundant multithreading processor is presented. In one embodiment, the processor performs execution of a thread and its duplicate thread in parallel and determines, when in a redundant multithreading mode, whether or not to synchronize an operation of the thread and an operation of the duplicate thread.
摘要翻译：介绍了冗余多线程处理器。在一个实施例中，处理器并行执行线程及其重复线程，并且在冗余多线程模式中确定是否同步线程的操作和复制线程的操作。

9. 发明授权

US08041754B1 Establishing thread priority in a processor or the like 有权
标题翻译：在处理器等中建立线程优先级
公开(公告)号：US08041754B1
公开(公告)日：2011-10-18
申请号：US09490172
申请日：2000-01-22
申请人： Deborah T. Marr
发明人： Deborah T. Marr
IPC分类号： G06F12/00 , G06F15/16 , G06F9/00 , G06F9/44 , G06F9/46
CPC分类号： G06F9/4881 , G06F9/5011 , G06F2209/507
摘要： In a multi-threaded processor, one or more variables are set up in memory (e.g., a register) to indicate which of a plurality of executable threads has a higher priority. Once the variable is set, several embodiments are presented for granting higher priority processing to the designated thread. For example, more instructions from the higher priority thread may be executed as compared to the lower priority thread. Also, a higher priority thread may be given comparatively more access to a given resource, such as memory or a bus.
摘要翻译：在多线程处理器中，在存储器（例如，寄存器）中设置一个或多个变量，以指示多个可执行线程中的哪一个具有较高优先级。一旦设置了变量，就呈现了几个实施例，用于向指定的线程授予更高优先级的处理。例如，与较低优先级线程相比，可以执行来自较高优先级线程的更多指令。此外，可以给予较高优先级的线程相对更多地访问诸如存储器或总线的给定资源。

10. 发明授权

US09569278B2 Asymmetric performance multicore architecture with same instruction set architecture 有权
标题翻译：具有相同指令集架构的不对称性能多核架构
公开(公告)号：US09569278B2
公开(公告)日：2017-02-14
申请号：US13335257
申请日：2011-12-22
申请人： Varghese George , Sanjeev S. Jahagirdar , Deborah T. Marr
发明人： Varghese George , Sanjeev S. Jahagirdar , Deborah T. Marr
IPC分类号： G06F9/50 , G06F1/32
CPC分类号： G06F15/80 , G06F1/3206 , G06F1/3293 , G06F1/3296 , G06F9/5094 , G06F13/4022 , Y02D10/122 , Y02D10/151 , Y02D10/22
摘要： A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.
摘要翻译：描述了一种方法，其涉及多核处理器的操作使能的核，使得两个核以相同的指令集支持相应的软件例程，第一核具有更高的性能并且在相同的一组应用供给下消耗比第二个核的更多的功率电压和工作频率。

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