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1. 发明授权

US08546240B2 Methods of manufacturing integrated semiconductor devices with single crystalline beam 有权
标题翻译：使用单晶束制造集成半导体器件的方法
公开(公告)号：US08546240B2
公开(公告)日：2013-10-01
申请号：US13294610
申请日：2011-11-11
申请人： David L. Harame , Stephen E. Luce , Anthony K. Stamper
发明人： David L. Harame , Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01L21/76 , H01L21/70
CPC分类号： H01L41/083 , G06F17/5068 , H01L21/84 , H01L27/1203 , H01L41/081 , H01L41/094 , H01L41/332 , H03H3/02 , H03H9/1007 , H03H9/173 , H03H2001/0064 , H03H2003/027 , H03H2009/155
摘要： Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes providing further sacrificial material in a trench of a lower wafer. The method further includes bonding the lower wafer to the insulator, under the single crystalline beam. The method further includes venting the sacrificial material and the further sacrificial material to form an upper cavity above the single crystalline beam and a lower cavity, below the single crystalline beam.
摘要翻译：提供了与CMOS器件集成的体声波滤波器和/或体声波谐振器，制造方法和设计结构。该方法包括从绝缘体上的硅层形成单晶束。该方法包括在单晶束上提供绝缘体材料涂层。该方法还包括通过绝缘体材料形成通孔。该方法还包括在通孔和绝缘体材料上提供牺牲材料。该方法还包括在牺牲材料上提供盖子。该方法还包括在下晶片的沟槽中提供另外的牺牲材料。该方法还包括在单晶束下将下晶片接合到绝缘体。该方法还包括排出牺牲材料和另外的牺牲材料，以在单晶束之下形成单结晶束上方的上空腔和在单晶束下方的下腔。

2. 发明申请

US20130256758A1 INTEGRATED CIRCUIT STRUCTURE HAVING AIR-GAP TRENCH ISOLATION AND RELATED DESIGN STRUCTURE 有权
标题翻译：具有空气阻隔层分离的集成电路结构及相关设计结构
公开(公告)号：US20130256758A1
公开(公告)日：2013-10-03
申请号：US13436045
申请日：2012-03-30
申请人： Renata A. Camillo-Castillo , James S. Dunn , David L. Harame , Anthony K. Stamper
发明人： Renata A. Camillo-Castillo , James S. Dunn , David L. Harame , Anthony K. Stamper
IPC分类号： H01L29/737 , H01L21/764
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/764 , H01L29/737
摘要： A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.
摘要翻译：形成集成电路结构的方法包括：通过延伸通过浅沟槽隔离（STI）形成通气孔并进入衬底; 在所述通气孔的底部选择性地去除所述衬底的暴露部分以在所述衬底内形成开口，其中所述衬底内的所述开口邻接所述STI的底表面或侧壁中的至少一个; 并密封通气孔以在基底内的开口中形成气隙。

3. 发明授权

US09105751B2 Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure 有权
标题翻译：具有单晶束的集成半导体器件，制造方法和设计结构
公开(公告)号：US09105751B2
公开(公告)日：2015-08-11
申请号：US13294603
申请日：2011-11-11
申请人： David L. Harame , Anthony K. Stamper
发明人： David L. Harame , Anthony K. Stamper
IPC分类号： H01L21/00 , H01L21/84 , H01L27/12 , H03H3/02 , H03H9/10 , H03H9/17 , H01L41/113 , H03H1/00 , H03H9/24 , H03H9/15
CPC分类号： B81B3/0027 , B81B2201/0285 , H01L21/84 , H01L27/1203 , H01L41/1136 , H01L2224/73265 , H03H3/02 , H03H9/1007 , H03H9/173 , H03H2001/0064 , H03H2003/027 , H03H2009/155 , H03H2009/241
摘要： Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam from a silicon layer on an insulator. The method further includes providing a coating of insulator material over the single crystalline beam. The method further includes forming a via through the insulator material exposing a wafer underlying the insulator. The insulator material remains over the single crystalline beam. The method further includes providing a sacrificial material in the via and over the insulator material. The method further includes providing a lid on the sacrificial material. The method further includes venting, through the lid, the sacrificial material and a portion of the wafer under the single crystalline beam to form an upper cavity above the single crystalline beam and a lower cavity in the wafer, below the single crystalline beam.
摘要翻译：提供了与CMOS器件集成的体声波滤波器和/或体声波谐振器，制造方法和设计结构。该方法包括从绝缘体上的硅层形成单晶束。该方法还包括在单晶束上提供绝缘体材料涂层。该方法还包括通过暴露出绝缘体下方的晶片的绝缘体材料形成通孔。绝缘体材料保留在单晶束上。该方法还包括在通孔和绝缘体材料上提供牺牲材料。该方法还包括在牺牲材料上提供盖子。该方法进一步包括通过盖子排出牺牲材料和在单一结晶束下方的晶片的一部分，以在单晶束之下形成单结晶束上方的上腔和晶片中的下腔。

4. 发明授权

US08603889B2 Integrated circuit structure having air-gap trench isolation and related design structure 有权
标题翻译：具有气隙沟槽隔离和相关设计结构的集成电路结构
公开(公告)号：US08603889B2
公开(公告)日：2013-12-10
申请号：US13436045
申请日：2012-03-30
申请人： Renata A. Camillo-Castillo , James S. Dunn , David L. Harame , Anthony K. Stamper
发明人： Renata A. Camillo-Castillo , James S. Dunn , David L. Harame , Anthony K. Stamper
IPC分类号： H01L21/78
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/764 , H01L29/737
摘要： A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.
摘要翻译：形成集成电路结构的方法包括：通过延伸通过浅沟槽隔离（STI）形成通气孔并进入衬底; 在所述通气孔的底部选择性地去除所述衬底的暴露部分以在所述衬底内形成开口，其中所述衬底内的所述开口邻接所述STI的底表面或侧壁中的至少一个; 并密封通气孔以在基底内的开口中形成气隙。

5. 发明申请

US20130119491A1 INTEGRATED SEMICONDUCTOR DEVICES WITH AMORPHOUS SILICON BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE 有权
标题翻译：具有非晶硅光束的集成半导体器件，制造方法和设计结构
公开(公告)号：US20130119491A1
公开(公告)日：2013-05-16
申请号：US13294615
申请日：2011-11-11
申请人： Stephen E. LUCE , Anthony K. Stamper
发明人： Stephen E. LUCE , Anthony K. Stamper
IPC分类号： H01L29/84 , G06F9/45 , H01L21/02
CPC分类号： H03H9/02007 , G06F17/5072 , H01L21/84 , H01L27/1203 , H03H3/02 , H03H9/1007 , H03H9/173 , H03H2001/0064 , H03H2003/027 , H03H2009/155
摘要： Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam comprising amorphous silicon material and providing an insulator material over and adjacent to the amorphous silicon beam. The method further includes forming a via through the insulator material and exposing a material underlying the amorphous silicon beam. The method further includes providing a sacrificial material in the via and over the amorphous silicon beam. The method further includes providing a lid on the sacrificial material and over the insulator material. The method further includes venting, through the lid, the sacrificial material and the underlying material to form an upper cavity above the amorphous silicon beam and a lower cavity below the amorphous silicon beam, respectively.
摘要翻译：公开了与CMOS工艺，制造方法和设计结构集成的体声波滤波器和/或体声波谐振器。该方法包括形成至少一个包含非晶硅材料的光束并在非晶硅光束上并邻近其提供绝缘体材料。该方法还包括通过绝缘体材料形成通孔并暴露非晶硅束下面的材料。该方法还包括在通孔和非晶硅光束上提供牺牲材料。该方法还包括在牺牲材料上并在绝缘体材料之上提供盖子。该方法还包括通过盖子排出牺牲材料和下面的材料，以分别在非晶硅束的上方形成上腔，并在非晶硅束的下方形成下腔。

6. 发明授权

US08211728B2 Horizontal micro-electro-mechanical-system switch 有权
标题翻译：水平微机电系统开关
公开(公告)号：US08211728B2
公开(公告)日：2012-07-03
申请号：US12632836
申请日：2009-12-08
申请人： Stephen E. Luce , Anthony K. Stamper
发明人： Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： H01L21/76838 , H01H59/0009
摘要： A first dielectric material layer and a second dielectric material layer are formed on a substrate. Three conductive portions are formed within the second dielectric material layer. An optional third dielectric material layer and an optional dielectric capping layer may be formed over the three conductive portions. Portions of the second dielectric material layer and the first dielectric material layer are removed from within an area of a hole in a masking layer. The first dielectric material layer is laterally undercut to provide a micro-electro-mechanical-system (MEMS) switch comprising a conductive cantilever, a conductive plate, and a conductive actuator from the three conductive portions as portions of the first and second dielectric material layers are removed. The MEMS switch may be employed to provide mechanical switchable contact between the conductive cantilever and the conductive plate through an electrical signal on the conductive actuator.
摘要翻译：第一介电材料层和第二电介质材料层形成在基板上。在第二介电材料层内形成三个导电部分。可以在三个导电部分上形成可选的第三介电材料层和可选的介电覆盖层。第二介质材料层和第一介电材料层的一部分从掩模层中的孔的区域内被去除。第一介电材料层被横向底切以提供微电子机械系统（MEMS）开关，其包括导电悬臂，导电板和导电致动器，作为第一和第二介电材料层的部分从三个导电部分被删除。 MEMS开关可用于通过导电致动器上的电信号在导电悬臂与导电板之间提供机械可切换接触。

7. 发明申请

US20090085152A1 THREE DIMENSIONAL VERTICAL E-FUSE STRUCTURES AND METHODS OF MANUFACTURING THE SAME 失效
标题翻译：三维垂直电子熔断器结构及其制造方法
公开(公告)号：US20090085152A1
公开(公告)日：2009-04-02
申请号：US11865079
申请日：2007-10-01
申请人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
发明人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01L23/62 , H01L21/44
CPC分类号： H01L23/5256 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.
摘要翻译：本文提供三维垂直电子熔丝结构及其制造方法。形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。垂直e熔丝结构包括第一接触层和第二接触层。该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。当施加电流时，导电材料具有增加的电阻。

8. 发明授权

US07015150B2 Exposed pore sealing post patterning 失效
标题翻译：曝露孔密封柱图案化
公开(公告)号：US07015150B2
公开(公告)日：2006-03-21
申请号：US10709747
申请日：2004-05-26
申请人： Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Stephen E. Luce , Thomas L. McDevitt , Lee M. Nicholson , Anthony K. Stamper
发明人： Edward C. Cooney, III , John A. Fitzsimmons , Jeffrey P. Gambino , Stephen E. Luce , Thomas L. McDevitt , Lee M. Nicholson , Anthony K. Stamper
IPC分类号： H01L21/31 , H01L21/302
CPC分类号： H01L21/76831 , H01L21/02107 , H01L21/02203 , H01L21/02337 , H01L21/0234 , H01L21/02362 , H01L21/3105 , H01L21/31116 , H01L21/31695 , H01L21/76802 , H01L21/76807 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76868
摘要： Methods and structures having pore-closing layers for closing exposed pores in a patterned porous low-k dielectric layer, and optionally a reactive liner on the low-k dielectric. A first reactant is absorbed or retained in exposed pores in the patterned dielectric layer and then a second reactant is introduced into openings such that it enters the exposed pores, while first reactant molecules are simultaneously being outgassed. The second reactant reacts in-situ with the outgassed first reactant molecules at a mouth region of the exposed pores to form the pore-closing layer across the mouth region of exposed pores, while retaining a portion of each pore's porosity to maintain characteristics and properties of the porous low-k dielectric layer. Optionally, the first reactant may be adsorbed onto the low-k dielectric such that upon introduction of the second reactant into the patterned dielectric openings, a reactive liner is also formed on the low-k dielectric.
摘要翻译：具有闭孔层的方法和结构，用于封闭图案化的多孔低k电介质层中的暴露孔，以及可选地在低k电介质上的反应性衬垫。第一反应物被吸收或保留在图案化介电层中的暴露孔中，然后将第二反应物引入开口中，使得其进入暴露的孔，同时第一反应物分子同时脱气。第二反应物与暴露孔的口部区域处的脱气的第一反应物分子原位反应，以形成穿过暴露孔的口部区域的孔闭合层，同时保留每个孔隙的一部分以保持其孔的特性和性质多孔低k电介质层。任选地，第一反应物可以被吸附到低k电介质上，使得当将第二反应物引入图案化的电介质开口中时，还在低k电介质上形成反应性衬垫。

9. 发明授权

US07087997B2 Copper to aluminum interlayer interconnect using stud and via liner 有权
公开(公告)号：US07087997B2
公开(公告)日：2006-08-08
申请号：US09805027
申请日：2001-03-12
申请人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
发明人： Lloyd G. Burrell , Edward E. Cooney, III , Jeffrey P. Gambino , John E. Heidenreich, III , Hyun Koo Lee , Mark D. Levy , Baozhen Li , Stephen E. Luce , Thomas L. McDevitt , Anthony K. Stamper , Kwong Hon Wong , Sally J. Yankee
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/76838 , H01L23/5226 , H01L23/53223 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

10. 发明授权

US08232190B2 Three dimensional vertical E-fuse structures and methods of manufacturing the same 失效
标题翻译：三维垂直E熔丝结构及其制造方法
公开(公告)号：US08232190B2
公开(公告)日：2012-07-31
申请号：US11865079
申请日：2007-10-01
申请人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
发明人： Kerry Bernstein , Timothy J. Dalton , Jeffrey P. Gambino , Mark D. Jaffe , Stephen E. Luce , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L23/5256 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.
摘要翻译：本文提供三维垂直电子熔丝结构及其制造方法。形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。垂直e熔丝结构包括第一接触层和第二接触层。该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。当施加电流时，导电材料具有增加的电阻。

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