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    • 1. 发明授权
    • Programmable servo burst decoder
    • 可编程伺服突发解码器
    • US5640583A
    • 1997-06-17
    • US293981
    • 1994-08-22
    • Nicolas C. AssouadJohn P. HillDavid L. Dyer
    • Nicolas C. AssouadJohn P. HillDavid L. Dyer
    • G11B5/596G11B20/10G11B27/30G06F7/00
    • G11B20/10G11B27/3027G11B5/59655G11B2020/1282
    • A disk drive controller integrated circuit includes a programmable servo burst decoder that can process any one of a plurality of servo sectors. A disk drive head reads each embedded servo sector on the disk and provides an analog signal, a servo burst, representing the servo sector to a preamp. The preamp provides an amplified analog signal to a read channel integrated circuit. The read channel integrated circuit provides input signals that are processed by the programmable servo burst decoder. The programmable servo burst decoder includes a programmable timing mark sequencer having an instruction register of a first size and a servo timing mark output line, and a programmable burst sequencer connected to the servo timing mark output line and having an instruction register of a second size. In this embodiment, the first size is different from the second size. Specifically, the first size is 20 bits, and the second size is 38 bits.
    • 磁盘驱动器控制器集成电路包括可处理多个伺服扇区中的任一个的可编程伺服突发解码器。 磁盘驱动器头读取磁盘上的每个嵌入式伺服扇区,并将表示伺服扇区的模拟信号,伺服脉冲串提供给前置放大器。 前置放大器为读通道集成电路提供放大的模拟信号。 读通道集成电路提供由可编程伺服脉冲解码器处理的输入信号。 可编程伺服脉冲串解码器包括具有第一大小的指令寄存器和伺服定时标记输出线的可编程定时标记定序器和连接到伺服定时标记输出线并具有第二大小的指令寄存器的可编程脉冲序列发生器。 在该实施例中,第一尺寸与第二尺寸不同。 具体来说,第一大小是20比特,第二大小是38比特。
    • 3. 发明授权
    • Dual function disk drive integrated circuit for master mode and slave
mode operations
    • 双功能磁盘驱动器集成电路,用于主模式和从模式操作
    • US5826093A
    • 1998-10-20
    • US363448
    • 1994-12-22
    • Nicolas C. AssouadDavid L. DyerThomas G. Adams
    • Nicolas C. AssouadDavid L. DyerThomas G. Adams
    • G06F3/06G06F15/78G06F15/00
    • G06F3/0607G06F15/7814G06F3/0634G06F3/0658G06F3/0676
    • A single integrated circuit includes an on-board processor, a peripheral port, and a general purpose input/output (I/O) circuit that support both master mode and slave mode operations. In a master mode of operation, the integrated circuit functions as a disk drive microcontroller and seamlessly interfaces with a hard disk controller. The integrated circuit includes programmable circuitry for generating individual chip select signals for external random access memory (RAM) and external read-only memory (ROM); a fully programmable general purpose input/output interface; and a programmable bi-directional peripheral port. Each of these features are utilized in the master mode to control operation of the disk drive. In a slave mode of operation, the integrated circuit provides full motion control of the spin and tracking systems of a disk drive. In slave mode, the peripheral port is an interface to a host microcontroller or a host RISC processor, that is typically contained within the disk drive. The host microcontroller communicates with the integrated circuit through a set of mailbox registers within the peripheral port to configure the integrated circuit for full motion control and to receive information from the integrated circuit.
    • 单个集成电路包括板载处理器,外围端口以及支持主模式和从模式操作的通用输入/输出(I / O)电路。 在主操作模式下,集成电路用作磁盘驱动器微控制器,并与硬盘控制器无缝连接。 集成电路包括用于产生用于外部随机存取存储器(RAM)和外部只读存储器(ROM)的单独芯片选择信号的可编程电路; 一个完全可编程的通用输入/输出接口; 和可编程双向外设端口。 这些特征中的每一个在主模式中被利用来控制磁盘驱动器的操作。 在从属操作模式下,集成电路为磁盘驱动器的自旋和跟踪系统提供全面的运动控制。 在从模式下,外设端口是主机微控制器或主机RISC处理器的接口,通常包含在磁盘驱动器中。 主机微控制器通过外围端口中的一组邮箱寄存器与集成电路进行通信,以配置集成电路进行全运动控制,并从集成电路接收信息。
    • 4. 发明授权
    • Hardware tracing/logging for highly integrated embedded controller device
    • 用于高度集成的嵌入式控制器设备的硬件跟踪/记录
    • US6119254A
    • 2000-09-12
    • US997130
    • 1997-12-23
    • Nicolas C. AssouadDavid L. DyerWen Lin
    • Nicolas C. AssouadDavid L. DyerWen Lin
    • G01R31/28G06F11/26
    • G06F11/261
    • A method of testing a processor controlled chip having embedded circuitry devoid of a direct connection external to said chip. Tracing circuitry embedded on the chip is programmed to detect the presence of specified information on a bus system embedded on the chip and devoid of a direct connection external to the chip. An address comparator detects the presence of the specified information on the bus system and opens gating circuitry in response to the detection. The specified information is extended through the gating circuitry and written in a buffer memory. The specified information can be read out of the buffer memory and extended to a user terminal external to the chip.
    • 一种测试具有嵌入式电路的处理器控制芯片的方法,所述嵌入式电路在所述芯片外部没有直接连接。 嵌入在芯片上的跟踪电路被编程为检测嵌入在芯片上的总线系统上的指定信息的存在,并且没有芯片外部的直接连接。 地址比较器检测总线系统上的指定信息的存在,并响应于检测而打开门控电路。 指定的信息通过门控电路扩展并写入缓冲存储器。 指定的信息可以从缓冲存储器中读出并扩展到芯片外部的用户终端。
    • 6. 发明授权
    • Programmable timing mark sequencer for a disk drive
    • 用于磁盘驱动器的可编程定时标记定序器
    • US5640538A
    • 1997-06-17
    • US294128
    • 1994-08-22
    • David L. DyerJohn P. HillNicolas C. Assouad
    • David L. DyerJohn P. HillNicolas C. Assouad
    • G11B5/596G06F17/00
    • G11B5/59616
    • A programmable timing mark sequencer automatically analyzes a sequence of data bits on a data input line. If the appropriate timing pattern is detected in the sequence of data bits, the timing mark sequencer drives a signal active on a servo timing mark output line. The timing mark sequencer is a fully programmable sequencer that is optimized for the detection of servo sector timing mark patterns. The timing mark sequencer includes a branch and fetch unit, a timing mark sequencer random access memory(RAM), an instruction register, a space counter, a window counter, and a synchronization flip-flop. The timing mark sequencer has a plurality of input lines including a search input line, a high resolution data bit line, and a decode clock line.
    • 可编程定时标记定序器自动分析数据输入线上的数据位序列。 如果在数据位序列中检测到适当的定时模式,则定时标记定序器驱动在伺服定时标记输出线上有效的信号。 定时标记定序器是一个完全可编程的定序器,针对伺服扇区定时标记模式的检测进行了优化。 定时标记定序器包括分支和取出单元,定时标记定序器随机存取存储器(RAM),指令寄存器,空间计数器,窗口计数器和同步触发器。 定时标记定序器具有包括搜索输入线,高分辨率数据位线和解码时钟线的多条输入线。