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1. 发明授权

US06677779B1 Flexible control interface for integrated circuit 有权
标题翻译：灵活的集成电路控制接口
公开(公告)号：US06677779B1
公开(公告)日：2004-01-13
申请号：US10113806
申请日：2002-03-28
申请人： David Kuochieh Su , Masoud Zargari , Lars E. Thon , William J. McFarland
发明人： David Kuochieh Su , Masoud Zargari , Lars E. Thon , William J. McFarland
IPC分类号： H03K19177
CPC分类号： G06F1/22 , G01R31/3167
摘要： A control interface, which includes both master and slave devices, can provide buffering of input data packets, thereby allowing configurations of the integrated circuit to be modified quickly and efficiently. Additionally, the control interface can be sized and configured to receive digital signals from any number of nodes on an integrated circuit, thereby facilitating the testing, lab characterization, and debugging of those nodes. Finally, the control interface can advatageously control the monitoring of analog components on the integrated circuit, thereby significantly reducing the number of pins for such monitoring. The control interface has particular relevance to highly integrated circuits that utilize analog and/or mixed signals.
摘要翻译：包括主设备和从设备的控制接口可以提供输入数据分组的缓冲，从而允许快速且有效地修改集成电路的配置。此外，控制接口的大小和配置可以从集成电路上的任意数量的节点接收数字信号，从而便于这些节点的测试，实验室特征化和调试。最后，控制接口可以对集成电路上的模拟组件进行监控，从而显着减少用于此类监视的引脚数量。控制接口与使用模拟和/或混合信号的高度集成电路特别相关。

2. 发明授权

US08755756B1 Active cancellation of interference in a wireless communication system 失效
标题翻译：主动消除无线通信系统中的干扰
公开(公告)号：US08755756B1
公开(公告)日：2014-06-17
申请号：US12769536
申请日：2010-04-28
申请人： Ning Zhang , David Kuochieh Su , William J. McFarland , Chin-Hung Chen
发明人： Ning Zhang , David Kuochieh Su , William J. McFarland , Chin-Hung Chen
IPC分类号： H04B1/04
CPC分类号： H04B1/109 , H04B1/525
摘要： Various methods and corresponding active interference cancellation units are described. These methods and units can perform active interference cancellation in a system including multiple radios. Notably, signals from a first radio can be received as interference at a second radio. The described methods and units can provide interference conditioning, which manipulates an interference reference of the interference at the first radio to approximate an interference observed at the second radio. After tuning of the interference conditioning, the interference can be removed.
摘要翻译：描述各种方法和相应的主动干扰消除单元。这些方法和单元可以在包括多个无线电的系统中执行主动干扰消除。值得注意的是，来自第一无线电的信号可以作为第二无线电的干扰被接收。所描述的方法和单元可以提供干扰调节，其处理在第一无线电处的干扰的干扰参考以近似在第二无线电处观察到的干扰。在调谐干扰调节之后，可以去除干扰。

3. 发明授权

US08289086B2 Fractional and integer PLL architectures 有权
标题翻译：分数和整数PLL架构
公开(公告)号：US08289086B2
公开(公告)日：2012-10-16
申请号：US12415878
申请日：2009-03-31
申请人： Shuo-Wei Chen , David Kuochieh Su
发明人： Shuo-Wei Chen , David Kuochieh Su
IPC分类号： H03L7/085 , H03L7/089 , H03L7/099
CPC分类号： H03L7/0998 , H03K3/03 , H03K5/133 , H03K2005/00032 , H03K2005/00052 , H03L7/081 , H03L7/093 , H03L7/0991 , H03L7/0995 , H03L7/183 , H03L7/1974 , H03L2207/50
摘要： A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.
摘要翻译：数字分数PLL在使用数字累加器的数字VCO之前引入累积相位偏移，以实现分数比的分数部分。为了提供这种相位偏移，数字累加器可以集成分数分量＆Dgr; n。通过强制＆Dgr; n为零，PLL变为整数N PLL。可以使用去偏移时序配置来消除PLL的整数和分数计数器之间的任何时间不匹配。数字PLL可以通过重新使用频率输出的各个相位来将频率产生（DVCO）的功能和分数频率计数的功能合并到相同的电路块中，以产生分数频率计数。数字整数PLL可以包括单比特比较器，其中该PLL的反馈环路迫使参考时钟信号和反馈信号之间的相位差接近零。通过改变反馈信号的占空比，可以改变回路的频率跟踪行为。

4. 发明申请

US20120223850A1 NON-UNIFORM SAMPLING TECHNIQUE USING A VOLTAGE CONTROLLED OSCILLATOR 有权
标题翻译：使用电压控制振荡器的非均匀采样技术
公开(公告)号：US20120223850A1
公开(公告)日：2012-09-06
申请号：US13040142
申请日：2011-03-03
申请人： David Kuochieh Su
发明人： David Kuochieh Su
IPC分类号： H03M1/00 , H03M1/66
CPC分类号： H03M1/1265 , H03M1/48
摘要： A data converter circuit includes a non-uniform sampling circuit and a resampler circuit. The non-uniform sampling circuit includes a sampling voltage-controlled oscillator (VCO) having an input to receive an analog data signal and having an output to generate a quantized data signal, wherein the quantized data signal comprises a plurality of non-uniform transition intervals indicative of data contained in the analog data signal. The resampling circuit has an input to receive the quantized data signal and is configured to reconstruct the data from the quantized data signal. For some embodiments, the data converter can also include a PLL that includes a feedback VCO having matched components with the sampling VCO.
摘要翻译：数据转换器电路包括非均匀采样电路和重采样电路。非均匀采样电路包括采样压控振荡器（VCO），其具有用于接收模拟数据信号并具有产生量化数据信号的输出的输入，其中量化数据信号包括多个不均匀的过渡间隔指示包含在模拟数据信号中的数据。重采样电路具有用于接收量化数据信号的输入，并被配置为从量化数据信号重构数据。对于一些实施例，数据转换器还可以包括PLL，其包括具有与采样VCO相匹配的分量的反馈VCO。

5. 发明授权

US06597227B1 System for providing electrostatic discharge protection for high-speed integrated circuits 有权
公开(公告)号：US06597227B1
公开(公告)日：2003-07-22
申请号：US09488940
申请日：2000-01-21
申请人： Chik Patrick Yue , Siu-Weng Simon Wong , David Kuochieh Su , William John McFarland
发明人： Chik Patrick Yue , Siu-Weng Simon Wong , David Kuochieh Su , William John McFarland
IPC分类号： H02H320
CPC分类号： H01L23/60 , H01L23/645 , H01L24/48 , H01L24/49 , H01L27/0248 , H01L2223/6611 , H01L2224/05554 , H01L2224/48091 , H01L2224/49113 , H01L2924/00014 , H01L2924/01039 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

6. 发明授权

US06593794B2 System for providing electrostatic discharge protection for high-speed integrated circuits 有权
公开(公告)号：US06593794B2
公开(公告)日：2003-07-15
申请号：US10072132
申请日：2002-02-07
申请人： Chik Patrick Yue , Siu-Weng Simon Wong , David Kuochieh Su , William John McFarland
发明人： Chik Patrick Yue , Siu-Weng Simon Wong , David Kuochieh Su , William John McFarland
IPC分类号： H03K508
CPC分类号： H01L23/60 , H01L23/645 , H01L24/48 , H01L24/49 , H01L27/0248 , H01L2223/6611 , H01L2224/05554 , H01L2224/48091 , H01L2224/49113 , H01L2924/00014 , H01L2924/01039 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

7. 发明授权

US08400341B2 Non-uniform sampling technique using a voltage controlled oscillator 有权
标题翻译：使用压控振荡器的非均匀采样技术
公开(公告)号：US08400341B2
公开(公告)日：2013-03-19
申请号：US13040142
申请日：2011-03-03
申请人： David Kuochieh Su
发明人： David Kuochieh Su
IPC分类号： H03M1/12
CPC分类号： H03M1/1265 , H03M1/48
摘要： A data converter circuit includes a non-uniform sampling circuit and a resampler circuit. The non-uniform sampling circuit includes a sampling voltage-controlled oscillator (VCO) having an input to receive an analog data signal and having an output to generate a quantized data signal, wherein the quantized data signal comprises a plurality of non-uniform transition intervals indicative of data contained in the analog data signal. The resampling circuit has an input to receive the quantized data signal and is configured to reconstruct the data from the quantized data signal. For some embodiments, the data converter can also include a PLL that includes a feedback VCO having matched components with the sampling VCO.
摘要翻译：数据转换器电路包括非均匀采样电路和重采样电路。非均匀采样电路包括采样压控振荡器（VCO），其具有用于接收模拟数据信号并具有产生量化数据信号的输出的输入，其中量化数据信号包括多个不均匀的过渡间隔指示包含在模拟数据信号中的数据。重采样电路具有用于接收量化数据信号的输入，并被配置为从量化数据信号重构数据。对于一些实施例，数据转换器还可以包括PLL，其包括具有与采样VCO相匹配的分量的反馈VCO。

8. 发明申请

US20090251225A1 Fractional And Integer PLL Architectures 有权
标题翻译：分数和整数PLL架构
公开(公告)号：US20090251225A1
公开(公告)日：2009-10-08
申请号：US12415878
申请日：2009-03-31
申请人： Shuo-Wei Chen , David Kuochieh Su
发明人： Shuo-Wei Chen , David Kuochieh Su
IPC分类号： H03L7/099 , H03K3/03
CPC分类号： H03L7/0998 , H03K3/03 , H03K5/133 , H03K2005/00032 , H03K2005/00052 , H03L7/081 , H03L7/093 , H03L7/0991 , H03L7/0995 , H03L7/183 , H03L7/1974 , H03L2207/50
摘要： A digital fractional PLL introduces an accumulated phase offset before the digital VCO using a digital accumulator to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a single bit comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock signal and the feedback signal to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.
摘要翻译：数字分数PLL在使用数字累加器的数字VCO之前引入累积相位偏移，以实现分数比的分数部分。为了提供这种相位偏移，数字累加器可以集成分数分量Deltan。通过强制Deltan为零，PLL变为整数N PLL。可以使用去偏移时序配置来消除PLL的整数和分数计数器之间的任何时间不匹配。数字PLL可以通过重新使用频率输出的各个相位来将频率产生（DVCO）的功能和分数频率计数的功能合并到相同的电路块中，以产生分数频率计数。数字整数PLL可以包括单比特比较器，其中该PLL的反馈环路迫使参考时钟信号和反馈信号之间的相位差接近零。通过改变反馈信号的占空比，可以改变回路的频率跟踪行为。

9. 发明授权

US06509779B2 System for providing electrostatic discharge protection for high-speed integrated circuits 有权
公开(公告)号：US06509779B2
公开(公告)日：2003-01-21
申请号：US10072191
申请日：2002-02-07
申请人： Chik Patrick Yue , Siu-Weng Simon Wong , David Kuochieh Su , William John McFarland
发明人： Chik Patrick Yue , Siu-Weng Simon Wong , David Kuochieh Su , William John McFarland
IPC分类号： H03K508
CPC分类号： H01L23/60 , H01L23/645 , H01L24/48 , H01L24/49 , H01L27/0248 , H01L2223/6611 , H01L2224/05554 , H01L2224/48091 , H01L2224/49113 , H01L2924/00014 , H01L2924/01039 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.

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