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    • 1. 发明申请
    • Layout quality analyzer
    • 布局质量分析仪
    • US20050132318A1
    • 2005-06-16
    • US11046071
    • 2005-01-28
    • David KiddNathan DiasMatthew Page
    • David KiddNathan DiasMatthew Page
    • G06F17/50
    • G06F17/5077
    • In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and represents a theoretically optimal route of the respective net according to a graph theory based algorithm. The second instructions, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. A method is also contemplated.
    • 在一个实施例中,计算机可读介质至少包括第一指令和第二指令。 第一指令在执行时计算第一组多个路由。 第一多个路线的每个路线对应于集成电路布局中的多个网络的相应网络,并且根据基于图论的算法表示相应网络的理论上最佳的路由。 所述第二指令在执行时将所述第一多个路由中的每一个与当前多个路由的对应路由进行比较,所述多个路由中的每一条路由对应于所述多个网络的相应网络,并且当前存在于所述集成电路中 布局。 也考虑了一种方法。
    • 2. 发明申请
    • Timing path detailer
    • 定时路径细节
    • US20050039152A1
    • 2005-02-17
    • US10949977
    • 2004-09-24
    • David KiddMatthew Page
    • David KiddMatthew Page
    • G06F17/50G06F9/45
    • G06F17/5031
    • A method (and a computer accessible medium comprising one or more instructions which, when executed, implement the method) is contemplated. At least a first timing path is identified in a first timing report corresponding to a first partition of a circuit. For at least one timing constraint applied to the first timing path, a second timing path in a second partition of the circuit that causes the timing constraint is determined. A second timing report comprising the first timing path from the first timing report and the second timing path from the second partition is generated.
    • 一种方法(以及包括一个或多个指令的计算机可访问介质,当被执行时执行该方法)。 在对应于电路的第一分区的第一定时报告中识别至少第一定时路径。 对于施加到第一定时路径的至少一个定时约束,确定引起定时约束的电路的第二分区中的第二定时路径。 生成包括来自第一定时报告的第一定时路径和来自第二分区的第二定时路径的第二定时报告。