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1. 发明申请

US20140344596A1 Controlling Power Consumption Of A Processor Using Interrupt-Mediated On-Off Keying 有权
标题翻译：使用中断介入开关键控制处理器的功耗
公开(公告)号：US20140344596A1
公开(公告)日：2014-11-20
申请号：US13894642
申请日：2013-05-15
申请人： David Keppel , Jawad Nasrullah
发明人： David Keppel , Jawad Nasrullah
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3206 , G06F1/3287 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the on and off times vary depending on whether and when an interrupt is incurred. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括一个逻辑，用于使得至少一个核心根据ON-OFF密钥协议的功率控制周期进行操作，所述功率控制周期包括多个接通时间和多个关闭时间，其中开启和关闭时间变化取决于是否和何时产生中断。描述和要求保护其他实施例。

2. 发明申请

US20120151235A1 METHODS AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENTRY AND EXIT LATENCY REDUCTION FOR LOW POWER STATES 有权
标题翻译：能源效率和能源节约的方法和系统，包括进入和退出低功耗状态的减排
公开(公告)号：US20120151235A1
公开(公告)日：2012-06-14
申请号：US13333753
申请日：2011-12-21
申请人： Jawad Nasrullah , Kelvin Kwan , Jaydeep P. Kulkarni , Muhammad M. Khellah
发明人： Jawad Nasrullah , Kelvin Kwan , Jaydeep P. Kulkarni , Muhammad M. Khellah
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.
摘要翻译：描述了用于低功率状态的进入和退出延迟降低的系统和方法。在一个实施例中，计算机实现的方法发起节能低功率状态（例如，深度睡眠状态）以减少设备的功耗。该方法设置电源电压，为双电源阵列提供足够的电力以保持状态。逻辑在此低功耗状态下掉电。

3. 发明申请

US20100159662A1 RAISED SOURCE/DRAIN WITH SUPER STEEP RETROGRADE CHANNEL 有权
标题翻译：提高来源/超级超级通道的排水
公开(公告)号：US20100159662A1
公开(公告)日：2010-06-24
申请号：US12715262
申请日：2010-03-01
申请人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
发明人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L29/1033 , H01L29/1083 , H01L29/7833
摘要： Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
摘要翻译：具有超陡逆行通道的升高源/漏源的系统和方法。根据本发明的第一实施例，在一个实施例中，半导体器件包括包括表面的衬底和设置在包括栅极氧化物厚度的表面上方的栅极氧化物。半导体器件还包括形成在表面下方深度的超陡逆行通道区域。深度约为栅极氧化物厚度的十至三十倍。根据一个实施例的实施例可以提供比常规技术中可用的更理想的主体偏置电压到阈值电压特性。

4. 发明授权

US08003471B2 Formation of a super steep retrograde channel 有权
标题翻译：形成一个超级陡峭的逆行通道
公开(公告)号：US08003471B2
公开(公告)日：2011-08-23
申请号：US12715262
申请日：2010-03-01
申请人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
发明人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L29/1033 , H01L29/1083 , H01L29/7833
摘要： Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with one embodiment may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
摘要翻译：具有超陡逆行通道的升高源/漏源的系统和方法。根据本发明的第一实施例，在一个实施例中，半导体器件包括包括表面的衬底和设置在包括栅极氧化物厚度的表面上方的栅极氧化物。半导体器件还包括形成在表面下方深度的超陡逆行通道区域。深度约为栅极氧化物厚度的十至三十倍。根据一个实施例的实施例可以提供比常规技术中可用的更理想的主体偏置电压到阈值电压特性。

5. 发明授权

US07068065B1 System and method for dynamic impedance matching 失效
标题翻译：动态阻抗匹配的系统和方法
公开(公告)号：US07068065B1
公开(公告)日：2006-06-27
申请号：US10830339
申请日：2004-04-22
申请人： Jawad Nasrullah
发明人： Jawad Nasrullah
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： An integrated circuit provides dynamic, on chip resistor trimming, including a digital control loop for stabilizing impedance matching among multiple devices communicatively linked over a data transmission line. The digital control loop stabilizes input/output impedance matching of various devices to within a precise ohmic range that is far narrower than standard process variations, such as sheet resistance, within the components themselves. The impedance matching circuit also overcomes EMI problems normally associated with digital control and thus provides dynamic on-chip digital control without non-linearity and with tighter tolerance than is presently possible. Accordingly, the circuit boosts performance of peripheral devices that communicate over a standard USB port, without the need for a computer as a go between or intermediate interface. This makes device to device communication possible as between USB On-the-Go capable devices.
摘要翻译：集成电路提供动态片上电阻微调，包括数字控制回路，用于稳定通过数据传输线通信连接的多个设备之间的阻抗匹配。数字控制回路将各种器件的输入/输出阻抗匹配稳定在精确的欧姆范围内，该精确的欧姆范围比组件本身内的标准工艺变化（如薄层电阻）要窄得多。阻抗匹配电路还克服了通常与数字控制相关的EMI问题，从而提供动态的片上数字控制，无需非线性并且比目前可能的更严格的公差。因此，该电路提高了通过标准USB端口进行通信的外围设备的性能，而不需要计算机作为中间接口之间或中间接口。这使得设备到设备之间的通信成为USB On-the-Go设备之间的可能。

6. 发明授权

US09665144B2 Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states 有权
公开(公告)号：US09665144B2
公开(公告)日：2017-05-30
申请号：US13333753
申请日：2011-12-21
申请人： Jawad Nasrullah , Kelvin Kwan , Jaydeep P. Kulkarni , Muhammad M. Khellah
发明人： Jawad Nasrullah , Kelvin Kwan , Jaydeep P. Kulkarni , Muhammad M. Khellah
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.

7. 发明授权

US09280190B2 Method and systems for energy efficiency and energy conservation including on-off keying for power control 有权
标题翻译：能效节能方法和系统，包括电源控制的开关键控
公开(公告)号：US09280190B2
公开(公告)日：2016-03-08
申请号：US13333759
申请日：2011-12-21
申请人： Jawad Nasrullah , Kelvin Kwan , David Roger Ditzel , Vjekoslav Svilan
发明人： Jawad Nasrullah , Kelvin Kwan , David Roger Ditzel , Vjekoslav Svilan
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3234 , G06F1/26 , G06F1/3203 , G06F1/3231 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/173
摘要： Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.
摘要翻译：描述了利用电源管理软件来控制设备功率的系统和方法。在一个实施例中，计算机实现的方法启动具有ON-OFF键控的功率控制，以控制用于能量效率和节能的设备的功率消耗。计算设备的ON-OFF键控的ON-OFF周期。该方法基于ON-OFF键控设置设备的目标频率，目标电源电压和电源门控制。

8. 发明申请

US20110300681A1 RAISED SOURCE/DRAIN WITH SUPER STEEP RETROGRADE CHANNEL 有权
标题翻译：提高来源/超级超级通道的排水
公开(公告)号：US20110300681A1
公开(公告)日：2011-12-08
申请号：US13214593
申请日：2011-08-22
申请人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
发明人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L29/1033 , H01L29/1083 , H01L29/7833
摘要： Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
摘要翻译：描述了具有超陡逆行通道的升高源极/漏极的系统和方法。根据第一实施例，半导体器件包括包括表面的衬底和设置在包括栅极氧化物厚度的表面之上的栅极氧化物。半导体器件还包括形成在表面下方深度的超陡逆行通道区域。深度约为栅极氧化物厚度的十至三十倍。实施例可以提供比常规技术中可获得的阈值电压特性更理想的主体偏置电压。

9. 发明授权

US09229872B2 Semiconductor chip with adaptive BIST cache testing during runtime 有权
标题翻译：半导体芯片在运行时具有自适应BIST缓存测试
公开(公告)号：US09229872B2
公开(公告)日：2016-01-05
申请号：US13843639
申请日：2013-03-15
申请人： Christopher Wilkerson , Jawad Nasrullah , Kelvin Kwan
发明人： Christopher Wilkerson , Jawad Nasrullah , Kelvin Kwan
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G01R31/31724 , G01R31/3187 , G06F1/3275 , G06F1/3296 , G06F11/2221 , G06F11/27 , G06F2212/601 , G11C29/16 , G11C2029/0401 , G11C2029/0409 , Y02D10/14 , Y02D10/172
摘要： A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.
摘要翻译：描述了在半导体管芯的运行时间期间包括嵌入在管芯上的存储部件的下一个BIST测试序列是适当的方法。该方法还包括将BIST测试序列应用于存储组件中的每个有效条目。该方法还包括将存储组件中的任何新无效条目标记为无效，并为每个新无效条目配置相应的替换条目。

10. 发明申请

US20140281602A1 Controlling Processor Consumption Using On-Off Keying Having A Maximum Off Time 有权
标题翻译：控制处理器消耗使用开关键控最大关闭时间
公开(公告)号：US20140281602A1
公开(公告)日：2014-09-18
申请号：US13827738
申请日：2013-03-14
申请人： David Pardo Keppel , Jawad Nasrullah
发明人： David Pardo Keppel , Jawad Nasrullah
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/324 , G06F1/3246 , G06F1/3287 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括使得至少一个核心根据ON-OFF密钥协议的功率控制周期进行操作的逻辑，所述功率控制周期包括多个接通时间和多个关闭时间，其中关闭时间各自对应于包括处理器的平台的最大关闭时间。描述和要求保护其他实施例。

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