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1. 发明授权

US4881165A Method and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systems 失效
标题翻译：在两个系统之间进行高速数据传输的方法和装置，在两个系统之间的时钟中以相同的时钟运行，具有未知的和不恒定的偏差
公开(公告)号：US4881165A
公开(公告)日：1989-11-14
申请号：US176474
申请日：1988-04-01
申请人： David J. Sager , Anne S. Valiton , Jay C. Stickney , Raj K. Ramanujan
发明人： David J. Sager , Anne S. Valiton , Jay C. Stickney , Raj K. Ramanujan
IPC分类号： G06F1/10 , G06F13/42
CPC分类号： G06F1/10 , G06F13/4217
摘要： The invention is directed to a method by which data from a first synchronous subsystem is transmitted to a second synchronous subsystem physically spaced from the first subsystem such that the system clock is skewed relative to the two subsystems. Pursuant to the invention, the transmitted data cycle time is multiple of the common system cycle time and a clock signal is forwarded with the data from the first subsystem to the second subsystem. The clock signal forwarded with the data provides an indication to the second subsystem of the instants of time at which received data changes. The data change instants are used to generate a binary signal that inverts its value at each such instant. The binary signal is transmitted through a synchronizer to produce a logic signal in the second subsystem. The logic signal is utilized to transmit the received data into the second subsystem in synchronization with the clock of the second subsystem.
摘要翻译：本发明涉及一种方法，通过该方法将来自第一同步子系统的数据传输到与第一子系统物理间隔的第二同步子系统，使得系统时钟相对于两个子系统偏斜。根据本发明，发送的数据周期时间是公共系统周期时间的倍数，并且时钟信号与从第一子系统到第二子系统的数据一起转发。用数据转发的时钟信号向第二子系统提供接收到的数据变化的时刻的指示。数据变化时刻用于产生在每个这样的时刻反转其值的二进制信号。二进制信号通过同步器传输，以在第二子系统中产生逻辑信号。逻辑信号用于与第二子系统的时钟同步地将接收的数据发送到第二子系统。

2. 发明授权

US5003459A Cache memory system 失效
标题翻译：缓存存储系统
公开(公告)号：US5003459A
公开(公告)日：1991-03-26
申请号：US176595
申请日：1988-04-01
申请人： Raj K. Ramanujan , Simon C. Steely, Jr. , Peter J. Bannon , David J. Sager
发明人： Raj K. Ramanujan , Simon C. Steely, Jr. , Peter J. Bannon , David J. Sager
IPC分类号： G06F12/10
CPC分类号： G06F12/1045
摘要： The invention is directed to a cache memory system in a data processor including a virtual cache memory, a physical cache memory, a virtual to physical translation buffer, a physical to virtual backmap, an Old-PA pointer and a lockout register. The backmap implements invalidates by clearing the valid flags in virtual cache memory. The Old-PA pointer indicates the backmap entry to be invalidated after a reference misses in the virtual cache. The physical address for data written to virtual cache memory is entered to Old-PA pointer by the translation buffer. The lockout register arrests all references to data which may have synonyms in virtual cache memory. The backmap is also used to invalidate any synonyms.
摘要翻译：本发明涉及包括虚拟高速缓冲存储器，物理高速缓冲存储器，虚拟到物理转换缓冲器，物理到虚拟背景图，旧PA指针和锁定寄存器的数据处理器中的高速缓冲存储器系统。反向映射通过清除虚拟高速缓存中的有效标志来实现无效。 Old-PA指针指示在虚拟缓存中的引用未命中之后，将无效的背景条目。写入虚拟高速缓冲存储器的数据的物理地址由转换缓冲区输入到旧PA指针。锁定寄存器阻止对虚拟高速缓冲存储器中可能具有同义词的数据的所有引用。背景图也用于使任何同义词无效。

3. 发明授权

US4825412A Lockout registers 失效
标题翻译：锁定寄存器
公开(公告)号：US4825412A
公开(公告)日：1989-04-25
申请号：US176448
申请日：1988-04-01
申请人： David J. Sager , Raj K. Ramanujan , Jeffrey L. Bell
发明人： David J. Sager , Raj K. Ramanujan , Jeffrey L. Bell
IPC分类号： G06F12/10 , G11C15/00
CPC分类号： G06F12/1045
摘要： A cache memory system in a data processor that has a main memory and a processing unit, the cache memory system including a virtually addressed storage cache. This virtually addressed storage cache is connected to the main memory for storing in storage cache locations preselected portions of data from the main memory. Each cache location includes a valid indicator to indicate the data in the cache location is current. A translation buffers is coupled to the storage cache, and translates a virtual address to a physical address. The backmap is coupled to the storage cache and the translation buffer, and invalidates data in the storage cache by generating an invalidate index to the cache location at which a valid indicator is to be cleared only when data in the storage cache is to be invalidated. The cache memory system includes at least one lockout register for storing addresses for data which may exist in more than one storage location. The backmap invalidates all copies of the data in the storage cache after every reference to data in the storage cache using an address in the lockout register.
摘要翻译：具有主存储器和处理单元的数据处理器中的高速缓冲存储器系统，所述高速缓存存储器系统包括虚拟地寻址的存储高速缓存。该虚拟寻址的存储高速缓存连接到主存储器，用于存储来自主存储器的数据的预选部分的存储缓存位置。每个高速缓存位置包括一个有效的指示符，以指示高速缓存位置中的数据是当前的。翻译缓冲器耦合到存储高速缓存，并将虚拟地址转换为物理地址。背景图被耦合到存储高速缓存和翻译缓冲器，并且通过仅在存储高速缓存中的数据被无效时，才通过生成有效指示符被清除的高速缓存位置的无效索引来使存储高速缓存中的数据无效。高速缓冲存储器系统包括至少一个锁定寄存器，用于存储可能存在于多于一个存储位置的数据的地址。每次使用锁定寄存器中的地址对存储缓存中的数据进行引用之后，后台映射将使存储缓存中的所有数据副本无效。

4. 发明申请

US20170185351A1 Non-uniform memory access latency adaptations to achieve bandwidth quality of service 审中-公开
公开(公告)号：US20170185351A1
公开(公告)日：2017-06-29
申请号：US14998085
申请日：2015-12-24
申请人： Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Raj K. Ramanujan , Brian J. Slechta
发明人： Francesc Guim Bernat , Karthik Kumar , Thomas Willhalm , Raj K. Ramanujan , Brian J. Slechta
IPC分类号： G06F3/06
CPC分类号： G06F12/0893 , G06F2212/1024 , G06F2212/603 , G06F2212/6042
摘要： Systems, apparatuses and methods may provide for detecting an issued request in a queue that is shared by a plurality of domains in a memory architecture, wherein the plurality of domains are associated with non-uniform access latencies. Additionally, a destination domain associated with the issued request may be determined. Moreover, a first set of additional requests may be prevented from being issued to the queue if the issued request satisfies an overrepresentation condition with respect to the destination domain and the first set of additional requests are associated with the destination domain. In one example, a second set of additional requests are permitted to be issued to the queue while the first set of additional requests are prevented from being issued to the queue, wherein the second set of additional requests are associated with one or more remaining domains in the plurality of domains.

5. 发明授权

US09418700B2 Bad block management mechanism 有权
标题翻译：坏块管理机制
公开(公告)号：US09418700B2
公开(公告)日：2016-08-16
申请号：US13537969
申请日：2012-06-29
申请人： Raj K. Ramanujan , Glenn J. Hinton , David J. Zimmerman
发明人： Raj K. Ramanujan , Glenn J. Hinton , David J. Zimmerman
IPC分类号： G11C29/00 , G11B20/18
CPC分类号： G11B20/1883 , G11C29/82 , G11C29/886
摘要： A system includes a non-volatile random access memory (NVRAM) device and controller logic that detects a bad block within the device, retires the bad block and replaces the bad block with a replacement block by assigning the address of the bad block to the replacement block.
摘要翻译：一种系统包括非易失性随机存取存储器（NVRAM）装置和控制器逻辑，用于检测装置内的坏块，通过将坏块的地址分配给替换来退出坏块并用替换块替换坏块块。

6. 发明申请

US20140006696A1 APPARATUS AND METHOD FOR PHASE CHANGE MEMORY DRIFT MANAGEMENT 有权
标题翻译：相位变化管理的设备和方法
公开(公告)号：US20140006696A1
公开(公告)日：2014-01-02
申请号：US13994116
申请日：2011-12-20
申请人： Raj K. Ramanujan , Mark A. Schmisseur
发明人： Raj K. Ramanujan , Mark A. Schmisseur
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/214 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/3418 , G11C2013/0054 , G11C2013/0057
摘要： A system and method are described for selecting a demarcation voltage for read and write operations. Embodiments of the invention provide a scheme to use multiple VDMs to cover the case where power-on drift is different from power-off drift of the PCMS cells. The controller automatically manages this through tracking refreshes and writes. In addition, the embodiments of the invention provide an efficient scheme to reduce the performance impact of the penalty box following a write by tracking recent write addresses through a hash-table or similar scheme. By way of example, a method in accordance with one embodiment comprises: detecting a read operation directed to a first block of a PCMS memory; determining whether a write operation has previously occurred to the first block within a specified amount of time prior to the read operation; using a first demarcation voltage (VDM) for the read operation if the write operation has previously occurred to the first block within the specified amount of time prior to the write operation; and using a second VDM for the read operation if the write operation has not previously occurred to the first block within the specified amount of time prior to the write or refresh operation.
摘要翻译：描述了用于选择用于读取和写入操作的分界电压的系统和方法。本发明的实施例提供了使用多个VDM来覆盖上电漂移与PCMS单元的断电漂移不同的情况的方案。控制器通过跟踪刷新和写入自动进行管理。此外，本发明的实施例提供了一种有效的方案，以通过通过散列表或类似方案跟踪最近的写入地址来减少写入之后的惩罚盒的性能影响。作为示例，根据一个实施例的方法包括：检测针对PCMS存储器的第一块的读取操作; 在所述读取操作之前的指定时间内确定是否先前对所述第一块发生了写入操作; 如果在写操作之前的指定时间内先前已经对第一块发生写操作，则使用第一分界电压（VDM）作为读操作; 以及如果在所述写入或刷新操作之前的所述指定时间量内的所述第一块以前没有发生写入操作，则使用第二VDM进行所述读取操作。

7. 发明授权

US08612676B2 Two-level system main memory 有权
标题翻译：二级系统主存
公开(公告)号：US08612676B2
公开(公告)日：2013-12-17
申请号：US12976545
申请日：2010-12-22
申请人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
发明人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
IPC分类号： G06F12/00
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0685 , G06F11/0766 , G06F12/0246 , G06F12/0638 , G06F12/0868 , G06F12/0893 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C14/009
摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
摘要翻译：本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。远存储器可以经由低带宽，高延迟装置耦合到CPU。

8. 发明申请

US20180089098A1 LOCAL AND REMOTE DUAL ADDRESS DECODING 审中-公开
公开(公告)号：US20180089098A1
公开(公告)日：2018-03-29
申请号：US15279319
申请日：2016-09-28
申请人： Francesc Cesc Guim Bernat , Kshitij A. Doshi , Steen Larsen , Mark A. Schmisseur , Raj K. Ramanujan
发明人： Francesc Cesc Guim Bernat , Kshitij A. Doshi , Steen Larsen , Mark A. Schmisseur , Raj K. Ramanujan
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/0813 , G06F12/1441 , G06F21/00 , G06F2212/1041 , G06F2212/657
摘要： Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more processors to generate a first memory request, the first memory request including a first address and a node identification, a caching agent coupled to the one or more processors, the caching agent to determine that the first address is homed to a remote node remote to the local node, a network interface controller (NIC) coupled to the caching agent, the NIC to produce a second memory request based on the first memory request, and the one or more processors further to receive a response to the second memory request, the response generated by a switch coupled to the NIC, the switch includes a remote system address decoder to determine a node identification to which the second memory request is homed.

9. 发明申请

US20170187805A1 Systems, Methods, and Apparatuses for Range Protection 审中-公开
公开(公告)号：US20170187805A1
公开(公告)日：2017-06-29
申请号：US14983087
申请日：2015-12-29
申请人： Francesc Guim Bernet , Karthik Kumar , Thomas Willhalm , Raj K. Ramanujan , Robert G. Blankenship
发明人： Francesc Guim Bernet , Karthik Kumar , Thomas Willhalm , Raj K. Ramanujan , Robert G. Blankenship
IPC分类号： H04L29/08 , G06F3/06 , G06F9/46
摘要： Systems, methods, and apparatuses for range protection. In some embodiments, an apparatus comprises at least one monitoring circuit to monitor for memory accesses to an address space and take action upon a violation to the address space, wherein the action is one of generating a notification to a node that requested the monitor, generating the wrong request, generate a notification in a specific context of the home node, and generating a notification in a node that has ownership of the address space; at least one a protection table to store an identifier of the address space; and at least one hardware core to execute an instruction to enable the monitoring circuit.

10. 发明申请

US20170180270A1 ADAPTIVE FABRIC MULTICAST SCHEMES 审中-公开
公开(公告)号：US20170180270A1
公开(公告)日：2017-06-22
申请号：US14973155
申请日：2015-12-17
申请人： Francesc Cesc Guim Bernat , Karthik KUMAR , Thomas Willhalm , Raj K. Ramanujan , Narayan Ranganathan
发明人： Francesc Cesc Guim Bernat , Karthik KUMAR , Thomas Willhalm , Raj K. Ramanujan , Narayan Ranganathan
IPC分类号： H04L12/931 , H04L12/26 , H04L1/00 , H04L12/927 , H04L12/18
CPC分类号： H04L49/201 , H04L12/1845 , H04L41/5006 , H04L43/10 , H04L47/806
摘要： Described herein are devices and techniques for distributing application data. A device can communicate with one or more hardware switches. The device can receive, from a software stack, a multicast message including a constraint that indicates how application data is to be distributed. The constraint including a listing of the set of nodes and a number of nodes to which the application data is to be distributed. The device may receive, from the software stack, the application data for distribution to a plurality of nodes. The plurality of nodes being a subset of the set of nodes equaling the number of nodes. The device may select the plurality of nodes from the set of nodes. The device also may distribute a copy of the application data to the plurality of nodes based on the constraint. Also described are other embodiments.

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