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1. 发明授权

US5983354A Method and apparatus for indication when a bus master is communicating with memory 失效
标题翻译：当总线主机与存储器通信时指示的方法和装置
公开(公告)号：US5983354A
公开(公告)日：1999-11-09
申请号：US984319
申请日：1997-12-03
申请人： David I. Poisner , Nima Homayoun , Sung Soo Cho
发明人： David I. Poisner , Nima Homayoun , Sung Soo Cho
IPC分类号： G06F13/16 , G06F1/32 , G06F12/00
CPC分类号： G06F13/1605 , Y02B60/1228
摘要： A method and apparatus for indicating when a device in a computer system is communicating with memory. Information is communicated between the device and memory in a manner that bypasses a bus. A side-band signal that indicates that this communication is transpiring is sent to a second device connected to the second bus. In response to this side-band signal, a bit in a register of the second device is set to a value that is then communicated by way of the second bus.
摘要翻译：一种用于指示计算机系统中的设备何时与存储器通信的方法和装置。以绕过总线的方式在设备和存储器之间传送信息。指示该通信正在发送的边带信号被发送到连接到第二总线的第二设备。响应于该边带信号，将第二设备的寄存器中的位设置为随后通过第二总线传送的值。

2. 发明授权

US6021506A Method and apparatus for stopping a bus clock while there are no activities on a bus 失效
标题翻译：在公共汽车没有活动的情况下停止总线时钟的方法和装置
公开(公告)号：US6021506A
公开(公告)日：2000-02-01
申请号：US127575
申请日：1998-07-31
申请人： Sung Soo Cho , Nima Homayoun
发明人： Sung Soo Cho , Nima Homayoun
IPC分类号： G06F1/32 , G06F1/10
CPC分类号： G06F1/3237 , G06F1/3203 , Y02B60/1221
摘要： A method and apparatus for stopping a bus clock when there are no activities present on a bus. In the illustrated embodiment, an AGP bus couples a graphics controller to core logic to transfer data between the two devices. A controller generates a first (AGP bus) clock signal CLK and a second (internal) clock signal iclk for the first and second devices. If the controller determines that there are no graphics activities on the AGP bus (i.e., the bus is idle), the controller issues a stop request to stop the internal clock signal iclk. The processing of the stop request is delayed for a period of seven cycles on the AGP bus clock CLK to await for an objection from either the graphics controller or the core logic. If an objection is received during the seven cycle delay, the internal clock iclk will not be stopped, and will continue to run. However, if an objection is not received, then the internal clock iclk will stop. If the graphics controller is in a low power or "sleep" state, the AGP bus clock CLK is stopped, thereby conserving power.
摘要翻译：一种在总线上没有活动时停止总线时钟的方法和装置。在所示实施例中，AGP总线将图形控制器耦合到核心逻辑以在两个设备之间传送数据。控制器产生用于第一和第二设备的第一（AGP总线）时钟信号CLK和第二（内部）时钟信号iclk。如果控制器确定AGP总线上没有图形活动（即总线空闲），则控制器发出停止请求以停止内部时钟信号iclk。停止请求的处理在AGP总线时钟CLK上延迟七个周期的周期，等待来自图形控制器或核心逻辑的异议。如果在七个周期延迟期间收到异议，内部时钟iclk将不会停止，并将继续运行。但是，如果没有收到异议，则内部时钟iclk将会停止。如果图形控制器处于低功耗或“休眠”状态，则停止AGP总线时钟CLK，从而节省功率。

3. 发明授权

US5671421A Serial interrupt bus protocol 失效
标题翻译：串行中断总线协议
公开(公告)号：US5671421A
公开(公告)日：1997-09-23
申请号：US351637
申请日：1994-12-07
申请人： James Kardach , Sung Soo Cho , Nicholas B. Peterson , Thomas R. Lane , Jayesh M. Joshi , Neil Songer
发明人： James Kardach , Sung Soo Cho , Nicholas B. Peterson , Thomas R. Lane , Jayesh M. Joshi , Neil Songer
IPC分类号： G06F13/24 , G06F9/46 , G06F13/14
CPC分类号： G06F13/24
摘要： A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.
摘要翻译：实现串行中断总线协议，其中计算机系统中的任何数量的外围设备可以向系统的中断控制器发出任何预定的中断信号，而不需要针对每个可能的中断的专用引脚。在串行中断总线上实现的每个外设都包含状态机逻辑，用于循环通过可能的中断状态。外设以串联中断控制器为起始和结束，该控制器遵循与系统外设相同的状态机器逻辑。当串行中断控制器接收到一个有效的中断信号时，根据中断控制器状态机逻辑的中断状态确定提供给系统中断控制器的中断信号。辅助串行中断总线上的外设可以通过系统中断桥与主系统中断总线上的外设串联链接，系统中断总线还包括状态机逻辑，用于跟随与系统外设相同的状态图。

4. 发明授权

US6161157A Docking system 有权
标题翻译：对接系统
公开(公告)号：US6161157A
公开(公告)日：2000-12-12
申请号：US179508
申请日：1998-10-27
申请人： Deepak Tripathi , Sung Soo Cho
发明人： Deepak Tripathi , Sung Soo Cho
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4045
摘要： A system includes a portable computer having a first bus and a docking base having a second bus. A serial link (e.g., a 1394 link) couples the portable computer to the docking base. The portable computer may include a controller to convert a first bus cycle targeted for the second bus to a serial cycle. The first and second buses may each include a Peripheral Component Interconnect (PCI) bus.
摘要翻译：系统包括具有第一总线的便携式计算机和具有第二总线的对接基座。串行链路（例如，1394链路）将便携式计算机耦合到对接基座。便携式计算机可以包括控制器，用于将针对第二总线的第一总线周期转换为串行周期。第一和第二总线可以各自包括外围部件互连（PCI）总线。

5. 发明授权

US6055372A Serial interrupt bus protocol 失效
标题翻译：串行中断总线协议
公开(公告)号：US6055372A
公开(公告)日：2000-04-25
申请号：US845634
申请日：1997-05-01
申请人： James Kardach , Sung Soo Cho , Nicholas B. Peterson , Thomas R Lane , Jayesh M. Joshi , Neil Songer
发明人： James Kardach , Sung Soo Cho , Nicholas B. Peterson , Thomas R Lane , Jayesh M. Joshi , Neil Songer
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.
摘要翻译：实现串行中断总线协议，其中计算机系统中的任何数量的外围设备可以向系统的中断控制器发出任何预定的中断信号，而不需要针对每个可能的中断的专用引脚。在串行中断总线上实现的每个外设都包含状态机逻辑，用于循环通过可能的中断状态。外设以串联中断控制器为起始和结束，该控制器遵循与系统外设相同的状态机器逻辑。当串行中断控制器接收到一个有效的中断信号时，根据中断控制器状态机逻辑的中断状态确定提供给系统中断控制器的中断信号。辅助串行中断总线上的外设可以通过系统中断桥与主系统中断总线上的外设串联链接，系统中断总线还包括状态机逻辑，用于跟随与系统外设相同的状态图。

6. 发明授权

US5862389A Method and apparatus for selectively invoking a particular interrupt service routine for a particular interrupt request 失效
标题翻译：用于选择性地调用特定中断请求的特定中断服务程序的方法和装置
公开(公告)号：US5862389A
公开(公告)日：1999-01-19
申请号：US778516
申请日：1997-01-03
申请人： James P. Kardach , Sung Soo Cho , Jayesh M. Joshi
发明人： James P. Kardach , Sung Soo Cho , Jayesh M. Joshi
IPC分类号： G06F9/48 , G06F13/24
CPC分类号： G06F9/4812 , G06F13/24
摘要： A circuit for selectively invoking a particular interrupt service routine to handle a particular interrupt request. The present invention includes a programmable register with one or more bits per interrupt request input. The present invention also includes interrupt selection logic which outputs a particular interrupt in response to an interrupt request input and data stored in the programmable register. The interrupt then invokes the associated interrupt service routine to handle the interrupt request. The present invention is used to choose the interrupt service routine to handle a particular interrupt request from any source within the computer system in any computer system operating mode.
摘要翻译：用于选择性地调用特定中断服务程序来处理特定中断请求的电路。本发明包括一个可编程寄存器，每个中断请求输入具有一个或多个位。本发明还包括响应于中断请求输入和存储在可编程寄存器中的数据输出特定中断的中断选择逻辑。然后中断调用相关的中断服务程序来处理中断请求。本发明用于在任何计算机系统操作模式中选择中断服务程序来处理来自计算机系统内的任何源的特定中断请求。

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