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1. 发明授权

US5219787A Trenching techniques for forming channels, vias and components in substrates 失效
标题翻译：用于在基底中形成通道，通孔和部件的沟槽技术
公开(公告)号：US5219787A
公开(公告)日：1993-06-15
申请号：US840428
申请日：1992-02-24
申请人： David H. Carey , Douglass A. Pietila , David M. Sigmond
发明人： David H. Carey , Douglass A. Pietila , David M. Sigmond
IPC分类号： H01L21/311 , H01L21/48 , H01L21/768 , H01L23/485 , H05K3/00 , H05K3/10 , H05K3/38 , H05K3/40 , H05K3/42 , H05K3/46
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/486 , H01L21/76804 , H01L23/485 , H05K3/0032 , H05K3/0041 , H05K3/005 , H01L2221/1026 , H01L2221/1031 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K2201/0166 , H05K2201/09563 , H05K2203/0108 , H05K2203/025 , H05K2203/0554 , H05K2203/0574 , H05K2203/107 , H05K2203/1189 , H05K3/0023 , H05K3/0035 , H05K3/107 , H05K3/388 , H05K3/4076 , H05K3/422 , H05K3/4644 , H05K3/4661
摘要： Trenching techniques for forming a channel partially through and a via completely through the insulating layer of a substrate are disclosed. With additional steps the channel can form an electrically conductive line, an electrode of an integrated capacitor, or an optical waveguide.
摘要翻译：公开了用于通过完全穿过衬底的绝缘层形成通道和通孔的沟槽的沟槽技术。通过附加步骤，通道可以形成导电线，集成电容器的电极或光波导。

2. 发明授权

US5101553A Method of making a metal-on-elastomer pressure contact connector 失效
标题翻译：制造金属弹性体压力接触连接器的方法
公开(公告)号：US5101553A
公开(公告)日：1992-04-07
申请号：US693264
申请日：1991-04-29
申请人： David H. Carey , David M. Sigmond
发明人： David H. Carey , David M. Sigmond
IPC分类号： H01R13/24 , H01R43/00
CPC分类号： H01R13/2435 , H01R12/714 , H01R43/007 , Y10T29/49218 , Y10T29/4922 , Y10T29/49993
摘要： A method of making a metal-on-elastomer pressure contact connector. The method includes embedding a plurality of parallel co-planar copper-beryllia wires comprising a plurality of coils in a silicone rubber elastomer with top and bottom surfaces, and removing metal from the tops and bottoms of the coils to form a pair of isolated wire filaments from each coil which extend from the top surface to the bottom surface of the elastomer. The filaments form arrays of electrical contacts above and below the elastomer exceeding 10,000 contacts per square inch.
摘要翻译：一种制造弹性体上的金属弹性体接触连接器的方法。该方法包括将包含多个线圈的多个平行的平行铜 - 黄铜线嵌入到具有顶表面和底表面的硅橡胶弹性体中，以及从线圈的顶部和底部去除金属以形成一对隔离的线丝从弹性体的顶表面延伸到底表面的每个线圈。长丝在弹性体上方和下方形成超过10,000个接触/平方英寸的电触头阵列。

3. 发明授权

US5240671A Method of forming recessed patterns in insulating substrates 失效
标题翻译：在绝缘基板上形成凹陷图案的方法
公开(公告)号：US5240671A
公开(公告)日：1993-08-31
申请号：US891029
申请日：1992-06-01
申请人： David H. Carey
发明人： David H. Carey
IPC分类号： B28B7/00 , B28B7/16 , B28B7/18 , C04B35/622 , C04B41/45 , C04B41/81 , H01L21/48 , H05K1/03 , H05K1/09 , H05K3/00 , H05K3/10 , H05K3/12
CPC分类号： C04B41/009 , B28B7/0064 , B28B7/16 , B28B7/18 , C04B35/622 , C04B41/4578 , C04B41/81 , H01L21/486 , H05K3/0014 , C04B2111/00844 , H05K1/0306 , H05K1/092 , H05K2201/09118 , H05K2203/1476 , H05K3/107 , H05K3/1258 , Y10T29/49163
摘要： A method of forming recessed patterns in insulators is described. One embodiment of the invention is directed to ceramic green sheet fabrication by providing a sculptured plastic tape mold which includes a floor, a plurality of sidewalls adjacent to and extending above the floor and a plurality of protrusions on and extending above the floor, casting a ceramic slurry into the mold such that the slurry contacts the floor, the sidewalls and the protrusions, and drying the slurry so as to produce a ceramic green sheet with a recessed pattern that replicates the shapes of the protrusions. The ceramic green sheet may be removed from the mold and filled with a conductor before firing; alternatively, the ceramic green sheet can be fired before removing the mold to form a rigid ceramic substrate which is then filled with a conductor.
摘要翻译：描述了在绝缘体中形成凹陷图案的方法。本发明的一个实施方案涉及通过提供一种雕刻的塑料带模具来提供陶瓷生片，所述模具包括地板，与地板相邻并在地板上方延伸的多个侧壁，以及在地板上方并在其上延伸的多个突起，铸造陶瓷浆料进入模具，使得浆料接触地板，侧壁和突起，并干燥浆料，以便产生具有复制突起形状的凹陷图案的陶瓷生片。陶瓷生片可以从模具中取出并在烧成之前用导体填充; 或者，可以在去除模具之前烧制陶瓷生片以形成刚性陶瓷衬底，然后填充导体。

4. 发明授权

US5091339A Trenching techniques for forming vias and channels in multilayer electrical interconnects 失效
标题翻译：用于在多层电气互连中形成通路和通道的沟槽技术
公开(公告)号：US5091339A
公开(公告)日：1992-02-25
申请号：US557427
申请日：1990-07-23
申请人： David H. Carey
发明人： David H. Carey
IPC分类号： H01L21/311 , H01L21/48 , H01L21/768 , H01L23/485 , H05K3/00 , H05K3/10 , H05K3/38 , H05K3/40 , H05K3/42 , H05K3/46
CPC分类号： H01L21/76817 , H01L21/31144 , H01L21/486 , H01L21/76804 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76813 , H01L23/485 , H05K3/0032 , H05K3/0041 , H05K3/005 , H01L2221/1031 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K2201/0166 , H05K2201/09563 , H05K2203/0108 , H05K2203/025 , H05K2203/0554 , H05K2203/0574 , H05K2203/1189 , H05K3/0023 , H05K3/0035 , H05K3/107 , H05K3/388 , H05K3/4076 , H05K3/422 , H05K3/4644 , H05K3/4661 , Y10S438/94 , Y10S438/945
摘要： Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.
摘要翻译：可以在相对较少的步骤中以低成本的蚀刻和图案化技术形成通过部分延伸的通孔和完全延伸穿过例如基板或集成电路的电互连中的绝缘层的通孔。然后可以以相对较少的步骤在通道和通孔中填充电导体。在一个实施例中，将通孔和通道暴露的不可侵蚀的硬掩模放置在聚酰亚胺层上，暴露通孔但覆盖通道的可侵蚀的软掩模置于硬掩模上，并施加等离子体蚀刻。蚀刻通孔区域直到软掩模完全侵蚀，然后蚀刻通孔区和通道区，以提供部分蚀刻的通道和完全蚀刻的通孔。此后，种子层沉积在互连上，并且导电层电解沉积在种子层上，基本上填充通道和通孔。然后通过抛光将互连表面平坦化，直到电导体仅保留在通道和通孔中。

5. 发明授权

US5173442A Methods of forming channels and vias in insulating layers 失效
标题翻译：在绝缘层中形成通道和通孔的方法
公开(公告)号：US5173442A
公开(公告)日：1992-12-22
申请号：US857011
申请日：1992-03-24
申请人： David H. Carey
发明人： David H. Carey
IPC分类号： H01L21/311 , H01L21/48 , H01L21/768 , H01L23/485 , H05K3/00 , H05K3/10 , H05K3/38 , H05K3/40 , H05K3/42 , H05K3/46
CPC分类号： H01L21/76817 , H01L21/31144 , H01L21/486 , H01L21/76804 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76813 , H01L23/485 , H05K3/0032 , H05K3/0041 , H05K3/005 , H01L2221/1031 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K2201/0166 , H05K2201/09563 , H05K2203/0108 , H05K2203/025 , H05K2203/0554 , H05K2203/0574 , H05K2203/107 , H05K2203/1189 , H05K3/0023 , H05K3/0035 , H05K3/107 , H05K3/388 , H05K3/4076 , H05K3/422 , H05K3/4644 , H05K3/4661 , Y10S438/94
摘要： Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias. The interconnect surface is then planarized by polishing until the electrical conductor remains only in the channels and vias.
摘要翻译：可以在相对较少的步骤中以低成本的蚀刻和图案化技术形成通过部分延伸的通孔和完全延伸穿过例如基板或集成电路的电互连中的绝缘层的通孔。然后可以以相对较少的步骤在通道和通孔中填充电导体。在一个实施例中，将通孔和通道暴露的不可侵蚀的硬掩模放置在聚酰亚胺层上，暴露通孔但覆盖通道的可侵蚀的软掩模放置在硬掩模上，并施加等离子体蚀刻。蚀刻通孔区域直到软掩模完全侵蚀，然后蚀刻通孔区和通道区，以提供部分蚀刻的通道和完全蚀刻的通孔。此后，种子层沉积在互连上，并且导电层电解沉积在种子层上，基本上填充通道和通孔。然后通过抛光将互连表面平坦化，直到电导体仅保留在通道和通孔中。

6. 发明授权

US4926241A Flip substrate for chip mount 失效
标题翻译：用于芯片安装的翻转衬底
公开(公告)号：US4926241A
公开(公告)日：1990-05-15
申请号：US157778
申请日：1988-02-19
申请人： David H. Carey
发明人： David H. Carey
IPC分类号： H05K3/46 , H01L23/538 , H05K1/11
CPC分类号： H01L23/5384 , H01L23/5383 , H01L2224/16 , H01L2224/16235 , H01L2224/73253 , H01L2924/01014 , H01L2924/01079 , H01L2924/09701 , H01L2924/15312 , H05K1/112
摘要： A substrate for attaching electrical devices having an interconnect wiring structure and a support for the interconnect, the support having a number of vias, or throughholes, extending therethrough and electrically connected to the interconnect. The substrate allows for attachment of the electrical devices on the side of the support opposite the interconnect at the vias, rather than on the interconnect itself. By so doing, the chips can be packed more densely since the area between the chips normally reserved for engineering change pads, test pads and the like is not required, these functions being performed on the interconnect on the opposite side of the substrate.

7. 发明授权

US5216803A Method and apparatus for removing bonded connections 失效
标题翻译：用于去除接合连接的方法和装置
公开(公告)号：US5216803A
公开(公告)日：1993-06-08
申请号：US805167
申请日：1991-12-11
申请人： Ernest R. Nolan , David H. Carey , Thomas A. Bishop
发明人： Ernest R. Nolan , David H. Carey , Thomas A. Bishop
IPC分类号： H05K13/04
CPC分类号： H05K13/0486 , Y10T29/49121 , Y10T29/49124 , Y10T29/49815 , Y10T29/49822 , Y10T29/53274
摘要： Removing welded outer lead bonds of TAB tape leads to contacts on a substrate. The method includes separating the electrical leads adjacent the weld bonds leaving a remnant, engaging the remnant with a shear tool, and moving the tool and bond relative to each other shearing the remnant. In some cases the tool is ultrasonically vibrated in a direction transversely to the relative movement of the tool and bond.
摘要翻译：去除TAB带焊接的外部引线接合导致衬底上的触点。该方法包括分离邻近焊缝的电引线留下残留物，用剪切工具接合残余物，并且相对于彼此移动工具和结合来剪切残余物。在一些情况下，该工具在横向于工具和结合的相对运动的方向上超声振动。

8. 发明授权

US5165166A Method of making a customizable circuitry 失效
标题翻译：制作可定制电路的方法
公开(公告)号：US5165166A
公开(公告)日：1992-11-24
申请号：US739344
申请日：1991-09-09
申请人： David H. Carey
发明人： David H. Carey
IPC分类号： H01L23/498 , H01L23/538 , H05K1/00
CPC分类号： H01L23/5383 , H01L23/4985 , H01L23/5382 , H05K1/0289 , H05K1/0298 , H01L2224/45124 , H01L2224/48091 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01039 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , Y10T29/49156 , Y10T29/49162
摘要： A customizable circuit using a programmable interconnect and a compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form along diagonal lines having a pitch determined by the basic wire segment length. The terminal ends of each of these segments are positioned in a plane such that the segments may be connected by short lengths to form the desired interconnect. The links which join the line segments represent the customization of the otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the integrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.
摘要翻译：使用可编程互连和兼容TAB芯片接合设计的可定制电路。可编程互连包括形成可编程结而不是连续导线的线段层。该分割使用每层中的线对线的偏移来执行，使得每层中的段的端部沿着具有由基本线段长度确定的间距的对角线形成。这些段中的每一个的末端位于一个平面中，使得该段可以通过短长度连接以形成所需的互连。连接线段的链接表示否定的未互连互连的定制。 TAB芯片接合设计使用载带将集成电路芯片连接到可编程互连。还公开了用于形成互连和TAB芯片接合设计的方法。

9. 发明授权

US5039628A Flip substrate for chip mount 失效
标题翻译：用于芯片安装的翻转衬底
公开(公告)号：US5039628A
公开(公告)日：1991-08-13
申请号：US479487
申请日：1990-02-12
申请人： David H. Carey
发明人： David H. Carey
IPC分类号： H01L23/538 , H05K1/11
CPC分类号： H01L23/5384 , H01L23/5383 , H01L2224/16225 , H01L2224/73253 , H01L2924/09701 , H05K1/112 , Y10T29/4913
摘要： A substrate for attaching electrical devices having an interconnect wiring structure and a support for the interconnect, the support having a number of vias, or throughholes, extending therethrough and electrically connected to the interconnect. The substrate allows for attachment of the electrical devices on the side of the support opposite the interconnect at the vias, rather than on the interconnect itself. By so doing, the chips can be packed more density since the area between the chips normally reserved for engineering change pads, test pads and the like is not required, these functions being performed on the interconnect on the opposite side of the substrate.
摘要翻译：一种用于附接具有互连布线结构的电气装置的基板和用于互连的支撑件，所述支撑件具有穿过其中并且电连接到所述互连件的多个通孔或通孔。基板允许电气装置在通孔的相对侧的支撑件的侧面上而不是在互连本身上附接。通过这样做，由于不需要通常保留用于工程改变焊盘，测试焊盘等的芯片之间的区域，所以芯片可以被更多地密封，这些功能在基板的相对侧上的互连上执行。

10. 发明授权

US5284548A Process for producing electrical circuits with precision surface features 失效
标题翻译：具有精密表面特征的电路生产工艺
公开(公告)号：US5284548A
公开(公告)日：1994-02-08
申请号：US25550
申请日：1993-03-03
申请人： David H. Carey , David J. Burger
发明人： David H. Carey , David J. Burger
IPC分类号： H05K3/06 , H05K3/10 , H05K3/38 , H05K3/42 , H05K3/46 , B44C1/22 , C23F1/00
CPC分类号： H05K3/4626 , H05K3/108 , H05K3/427 , H05K3/4655 , H05K2201/0154 , H05K2201/0195 , H05K2201/0347 , H05K2201/0355 , H05K2201/09581 , H05K2203/072 , H05K2203/1407 , H05K3/064 , H05K3/386 , H05K3/388 , H05K3/429 , H05K3/4611 , H05K3/4652
摘要： A process for producing fine pitch surface features on a multilayer printed circuit boards such as copper-polyimide interconnects without requiring a thick copper plating foil. Initially, a thin first conductor (less than 1 micron) is vacuum deposited on a dielectric base and the dielectric base is disposed on a substrate. The substrate is then laminated and through-holes are formed therethrough. A plating seed is deposited in the through-holes and resist is patterned on the first conductor. A second conductor is deposited on the exposed portions of the first conductor and on the sidewalls, the resist is stripped and the portions or the first conductor beneath the resist are removed using a brief wet chemical etch to form spaced features without significant undercut. In the preferred embodiment, vacuum deposition occurs in a continuous roll sputtering system.
摘要翻译：在多层印刷电路板（例如铜 - 聚酰亚胺互连）上生产细间距表面特征的方法，而不需要厚的镀铜箔。首先，将薄的第一导体（小于1微米）真空沉积在电介质基底上，并将电介质基底设置在基底上。然后层压基板，并且通过其形成通孔。电镀种子沉积在通孔中，抗蚀剂被图案化在第一导体上。第二导体沉积在第一导体的暴露部分上并且在侧壁上，剥离抗蚀剂，并且使用短暂的湿化学蚀刻去除抗蚀剂下面的部分或第一导体，以形成间隔的特征而没有显着的底切。在优选实施例中，在连续辊式溅射系统中发生真空沉积。

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