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1. 发明授权

US6076155A Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets 失效
标题翻译：用于双指令集CPU的共享寄存器架构，以便于指令集之间的数据交换
公开(公告)号：US6076155A
公开(公告)日：2000-06-13
申请号：US100273
申请日：1998-06-19
申请人： James S. Blomgren , David E. Richter
发明人： James S. Blomgren , David E. Richter
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/54
CPC分类号： G06F9/30189 , G06F9/30094 , G06F9/30123 , G06F9/3013 , G06F9/30174 , G06F9/30196
摘要： A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be to transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions. The RISC and CISC registers are folded together so that the CISC flags are at one end of the register while the frequently used RISC flags are at the other end, but the RISC instructions can read or write any bit in the merged register. The CISC code segment base address is stored in the RISC branch count register, while the CISC floating point instruction address is stored in the RISC branch link register. The general-purpose registers (GPR's) are also merged together, allowing a CISC program to pass data to a RISC program merely by writing one of its GPR's, switching control to the RISC program, and the RISC program reading one of its GPR's that is merged with and corresponds to the CISC GPR that was written to by the CISC program.
摘要翻译：双指令集中央处理单元（CPU）能够执行来自精简指令集计算机（RISC）指令集和复杂指令集计算机（CISC）指令集的指令。数据和地址信息可以通过使用共享寄存器从CISC程序传送到运行在CPU上的RISC程序。 CISC指令集中的体系结构定义的寄存器被合并或折叠成RISC架构中的一些体系结构定义的寄存器，以便这两个指令集共享这些合并的寄存器。特别地，由每个架构定义的标志或条件代码寄存器被合并在一起，使得当执行计算指令时，CISC指令和RISC指令将隐含地更新相同的合并的标志寄存器。 RISC和CISC寄存器被折叠在一起，使得CISC标志位于寄存器的一端，而频繁使用的RISC标志位于另一端，但RISC指令可以读或写合并寄存器中的任何位。 CISC代码段基地址存储在RISC分支计数寄存器中，而CISC浮点指令地址存储在RISC分支链路寄存器中。通用寄存器（GPR）也被合并在一起，允许CISC程序将数据传递到RISC程序，只需将其GPR，切换控制之一写入RISC程序，读取其中一个GPR的RISC程序即可与CISC程序写入的CISC GPR合并并对应。

2. 发明授权

US5781750A Dual-instruction-set architecture CPU with hidden software emulation mode 失效
标题翻译：双指令集架构CPU具有隐藏的软件仿真模式
公开(公告)号：US5781750A
公开(公告)日：1998-07-14
申请号：US179926
申请日：1994-01-11
申请人： James S. Blomgren , David E. Richter
发明人： James S. Blomgren , David E. Richter
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/455 , G06F12/02
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30167 , G06F9/30174 , G06F9/30185 , G06F9/30196 , G06F9/45533 , G06F12/0292
摘要： A dual-instruction-set CPU is able to execute x86 CISC (complex instruction set computer) code or PowerPC RISC (reduced instruction set computer) code. Three modes of operation are provided: CISC mode, RISC mode, both called user modes, and emulation mode. Emulation mode is entered upon reset, and performs various system checks and memory allocation. A special emulation driver is loaded into a portion of main memory set aside at reset. Software routines to emulate the more complex instructions of the CISC architecture using RISC instructions are also loaded into the emulation memory. A TLB is enabled, and translation tables and drivers are set up in the emulation memory. All TLB misses, even in the user modes, will cause entry to a translator driver in emulation mode. Since the TLB is always enabled for the user modes, and all misses are handled by the emulation code, the emulation code can set aside a portion of memory for itself and insure that the user programs never have access to the emulation memory. Thus the programs, including operating systems, in CISC or RISC mode are unaware of emulation memory or even the existence of emulation mode.
摘要翻译：双指令集CPU能够执行x86 CISC（复杂指令集计算机）代码或PowerPC RISC（精简指令集计算机）代码。提供三种操作模式：CISC模式，RISC模式，称为用户模式和仿真模式。复位后进入仿真模式，进行各种系统检查和存储器分配。一个特殊的仿真驱动程序被加载到重置的一部分主存储器中。仿真使用RISC指令的CISC架构更复杂的指令的软件例程也被加载到仿真存储器中。启用TLB，并在仿真存储器中设置转换表和驱动程序。即使在用户模式下，所有TLB都将丢失，将导致在仿真模式下进入转换驱动程序。由于对于用户模式始终启用TLB，并且所有未命中都由仿真代码处理，所以仿真代码可以为自己留出一部分存储器，并确保用户程序永远不能访问仿真存储器。因此，CISC或RISC模式下的程序（包括操作系统）不知道仿真存储器甚至是仿真模式的存在。

3. 发明授权

US5598553A Program watchpoint checking using paging with sub-page validity 失效
标题翻译：使用具有子页有效性的分页进行程序观察点检查
公开(公告)号：US5598553A
公开(公告)日：1997-01-28
申请号：US444813
申请日：1995-05-18
申请人： David E. Richter , Earl T. Cohen , James S. Blomgren
发明人： David E. Richter , Earl T. Cohen , James S. Blomgren
IPC分类号： G06F11/36 , G06F12/10 , G06F9/455
CPC分类号： G06F11/3648 , G06F12/1027 , G06F12/1036 , G06F12/109
摘要： Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is achieved by extending the paging system to allow for valid regions that are less than the full page size. Sub-page validity can mimic segmentation because a segment can be broken up into a number of full pages and one or more partially-valid pages at the segment boundaries. A page that is not wholly valid has an "event" on the page, and a memory reference to this page will either cause a software routine to be invoked to check the segment bound, or an extension to the TLB, called a sub-page validity buffer, is used to check if the reference was to a valid portion of the page. Events may also be defined for program watchpoints and defective memory locations. Segment bounds thus do not have to be compared for each access, and the bounds do not even have to be stored on the CPU die.
摘要翻译：分段被添加到支持寻呼的精简指令集计算机（RISC）处理器。扩展算术逻辑单元（ALU）以允许3端口添加，以便在生成虚拟地址时添加段基础。通过扩展分页系统来实现分段边界检查，以允许小于整页大小的有效区域。子页面有效性可以模拟分割，因为片段可以分割成多个完整页面和一个或多个部分有效页面在段边界。不完全有效的页面在页面上具有“事件”，并且对该页面的存储器引用将导致调用软件例程来检查段绑定，或者称为子页面的TLB的扩展有效性缓冲区，用于检查引用是否是页面的有效部分。事件也可以定义为程序观察点和缺陷记忆位置。因此，对于每个访问，段边界不必进行比较，并且边界甚至不必被存储在CPU管芯上。

4. 发明授权

US5652872A Translator having segment bounds encoding for storage in a TLB 失效
标题翻译：具有分段边界编码的转换器存储在TLB中
公开(公告)号：US5652872A
公开(公告)日：1997-07-29
申请号：US436137
申请日：1995-05-08
申请人： David E. Richter , James S. Blomgren
发明人： David E. Richter , James S. Blomgren
IPC分类号： G06F11/36 , G06F12/10
CPC分类号： G06F12/1027 , G06F11/3648 , G06F12/1036 , G06F12/109
摘要： A computer system emulates segment bounds checking with a paging system. Pages entirely within a segment are designated as `clear pages`, while the first and last pages containing segment bounds may be partially-valid pages. The computer system has a memory with a segment descriptor table and an active segment descriptor cache. The active segment descriptor cache holds a copy of the segment descriptors for the active segments in a central processing unit (CPU). The active segment descriptor cache also hold the first and last clear page numbers and the first and last linear address offsets for the active segment. A software segment load routine copies portions of the segment descriptor from the segment descriptor table to the active segment descriptor cache when a user program loads a new segment. Only the segment base address is copied to the CPU die; the segment limit and selector need not be stored on the CPU die. The CPU has a translation-lookaside buffer (TLB) that includes bounds fields and a comparator for signaling when an offset portion of a linear address is outside the bound on a page. A TLB miss routine compares the linear address to the first and last clear pages in the active segment descriptor cache and loads a fully-valid page if the linear address is between the first and last clear pages, but loads the bounds field with the page offset of the segment bound if the linear address is to a partial page at the bounds of the segment.
摘要翻译：计算机系统利用寻呼系统模拟分段边界检查。完全在片段内的页面被指定为“清除页面”，而包含分段边界的第一页和最后一页可能是部分有效的页面。计算机系统具有具有段描述符表和活动段描述符高速缓存的存储器。活动段描述符缓存在中央处理单元（CPU）中保存活动段的段描述符的副本。活动段描述符缓存还保存有效段的第一个和最后一个清除页码以及第一个和最后一个线性地址偏移量。当用户程序加载新的段时，软件段加载例程将段描述符的部分从段描述符表复制到活动段描述符高速缓存。只有段基地址被复制到CPU管芯; 段限制和选择器不需要存储在CPU管芯上。 CPU具有包括边界字段的翻译后备缓冲器（TLB）和用于当线性地址的偏移部分在页面上的边界之外的信令的比较器。 TLB miss例程将线性地址与活动段描述符缓存中的第一个和最后一个清除页面进行比较，如果线性地址位于第一个和最后一个清除页面之间，则加载完全有效的页面，但是将边界字段加载到页面偏移量如果线性地址是在段的边界处的部分页面，则该段被绑定。

5. 发明授权

US5481693A Shared register architecture for a dual-instruction-set CPU 失效
标题翻译：双指令集CPU的共享寄存器架构
公开(公告)号：US5481693A
公开(公告)日：1996-01-02
申请号：US277962
申请日：1994-07-20
申请人： James S. Blomgren , David E. Richter
发明人： James S. Blomgren , David E. Richter
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/455
CPC分类号： G06F9/30014 , G06F9/30094 , G06F9/30101 , G06F9/30112 , G06F9/3013 , G06F9/30174 , G06F9/3861 , G06F9/4555
摘要： A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions. The RISC and CISC registers are folded together so that the CISC flags are at one end of the register while the frequently used RISC flags are at the other end, but the RISC instructions can read or write any bit in the merged register. The CISC code segment base address is stored in the RISC branch count register, while the CISC floating point instruction address is stored in the RISC branch link register. The general-purpose registers (GPR's) are also merged together, allowing a CISC program to pass data to a RISC program merely by writing one of its GPR's, switching control to the RISC program, and the RISC program reading one of its GPR's that is merged with and corresponds to the CISC GPR that was written to by the CISC program.
摘要翻译：双指令集中央处理单元（CPU）能够执行来自精简指令集计算机（RISC）指令集和复杂指令集计算机（CISC）指令集的指令。数据和地址信息可以通过使用共享寄存器从CISC程序传送到运行在CPU上的RISC程序。 CISC指令集中的体系结构定义的寄存器被合并或折叠成RISC架构中的一些体系结构定义的寄存器，以便这两个指令集共享这些合并的寄存器。特别地，由每个架构定义的标志或条件代码寄存器被合并在一起，使得当执行计算指令时，CISC指令和RISC指令将隐含地更新相同的合并的标志寄存器。 RISC和CISC寄存器被折叠在一起，使得CISC标志位于寄存器的一端，而频繁使用的RISC标志位于另一端，但RISC指令可以读或写合并寄存器中的任何位。 CISC代码段基地址存储在RISC分支计数寄存器中，而CISC浮点指令地址存储在RISC分支链路寄存器中。通用寄存器（GPR）也被合并在一起，允许CISC程序将数据传递到RISC程序，只需将其GPR，切换控制之一写入RISC程序，读取其中一个GPR的RISC程序即可与CISC程序写入的CISC GPR合并并对应。

6. 发明授权

US5440710A Emulation of segment bounds checking using paging with sub-page validity 失效
标题翻译：使用具有子页有效性的分页来对段边界进行仿真
公开(公告)号：US5440710A
公开(公告)日：1995-08-08
申请号：US207857
申请日：1994-03-08
申请人： David E. Richter , Earl T. Cohen , James S. Blomgren
发明人： David E. Richter , Earl T. Cohen , James S. Blomgren
IPC分类号： G06F11/36 , G06F12/10
CPC分类号： G06F11/3648 , G06F12/1027 , G06F12/1036 , G06F12/109
摘要： Segmentation is added to a reduced instruction set computer (RISC) processor which supports paging. The arithmetic-logic-unit (ALU) is extended to allow for a 3-port addition so that the segment base can be added when the virtual address is being generated. Segment bounds checking is achieved by extending the paging system to allow for valid regions that are less than the full page size. Sub-page validity can mimic segmentation because a segment can be broken up into a number of full pages and one or more partially-valid pages at the segment boundaries. A page that is not wholly valid has an "event" on the page, and a memory reference to this page will either cause a software routine to be invoked to check the segment bound, or an extension to the TLB, called a sub-page validity buffer, is used to check if the reference was to a valid portion of the page. Events may also be defined for program watchpoints and defective memory locations. Segment bounds thus do not have to be compared for each access, and the bounds do not even have to be stored on the CPU die.
摘要翻译：分段被添加到支持寻呼的精简指令集计算机（RISC）处理器。扩展算术逻辑单元（ALU）以允许3端口添加，以便在生成虚拟地址时添加段基础。通过扩展分页系统来实现分段边界检查，以允许小于整页大小的有效区域。子页面有效性可以模拟分割，因为片段可以分割成多个完整页面和一个或多个部分有效页面在段边界。不完全有效的页面在页面上具有“事件”，并且对该页面的存储器引用将导致调用软件例程来检查段绑定，或者称为子页面的TLB的扩展有效性缓冲区，用于检查引用是否是页面的有效部分。事件也可以定义为程序观察点和缺陷记忆位置。因此，对于每个访问，段边界不必进行比较，并且边界甚至不必被存储在CPU管芯上。

7. 发明授权

US5848264A Debug and video queue for multi-processor chip 失效
标题翻译：多处理器芯片的调试和视频队列
公开(公告)号：US5848264A
公开(公告)日：1998-12-08
申请号：US740248
申请日：1996-10-25
申请人： Brian R. Baird , David E. Richter , Shalesh Thusoo , David M. Stark , James S. Blomgren
发明人： Brian R. Baird , David E. Richter , Shalesh Thusoo , David M. Stark , James S. Blomgren
IPC分类号： G06F11/36 , G06F9/455
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A microprocessor die contains several processor cores and a shared cache. Trigger conditions for one or more of the processor cores are programmed into debug registers. When a trigger is detected, a trace record is generated and loaded into a debug queue on the microprocessor die. Several trace records from different processor cores can be rapidly generated and loaded into the debug queue. The external interface cannot transfer these trace records to an external in-circuit emulator (ICE) at the rate generated. The debug queue transfers trace records to the external ICE using a dedicated bus to the ICE so that bandwidth is not taken from the memory bus. The memory bus is not slowed for debugging, providing a more realistic debugging session. The debug buffer is also used as a video FIFO for buffering pixels for display on a monitor. The dedicated bus is connected to an external DAC rather than to the external ICE when debugging is not being performed.
摘要翻译：微处理器芯片包含几个处理器内核和一个共享缓存。一个或多个处理器内核的触发条件被编程到调试寄存器中。当检测到触发时，生成跟踪记录并加载到微处理器管芯上的调试队列中。可以快速生成来自不同处理器内核的多个跟踪记录，并将其加载到调试队列中。外部接口不能以生成的速率将这些跟踪记录传输到外部在线仿真器（ICE）。调试队列使用专用总线将ICE跟踪记录传输到外部ICE，从而不会从存储器总线获取带宽。内存总线调试速度并不慢，提供了更实际的调试会话。调试缓冲区还用作视频FIFO，用于缓冲显示器上的像素。当不进行调试时，专用总线连接到外部DAC而不是外部ICE。

8. 发明授权

US5805918A Dual-instruction-set CPU having shared register for storing data before switching to the alternate instruction set 失效
标题翻译：双指令集CPU具有共享寄存器，用于在切换到备用指令集之前存储数据
公开(公告)号：US5805918A
公开(公告)日：1998-09-08
申请号：US547395
申请日：1995-10-24
申请人： James S. Blomgren , David E. Richter
发明人： James S. Blomgren , David E. Richter
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/455
CPC分类号： G06F9/30014 , G06F9/30094 , G06F9/30101 , G06F9/30112 , G06F9/3013 , G06F9/30174 , G06F9/3861 , G06F9/4555
摘要： A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions. The RISC and CISC registers are folded together so that the CISC flags are at one end of the register while the frequently used RISC flags are at the other end, but the RISC instructions can read or write any bit in the merged register. The CISC code segment base address is stored in the RISC branch count register, while the CISC floating point instruction address is stored in the RISC branch link register. The general-purpose registers (GPR's) are also merged together, allowing a CISC program to pass data to a RISC program merely by writing one of its GPR's, switching control to the RISC program, and the RISC program reading one of its GPR's that is merged with and corresponds to the CISC GPR that was written to by the CISC program.
摘要翻译：双指令集中央处理单元（CPU）能够执行来自精简指令集计算机（RISC）指令集和复杂指令集计算机（CISC）指令集的指令。数据和地址信息可以通过使用共享寄存器从CISC程序传送到运行在CPU上的RISC程序。 CISC指令集中的体系结构定义的寄存器被合并或折叠成RISC架构中的一些体系结构定义的寄存器，以便这两个指令集共享这些合并的寄存器。特别地，由每个架构定义的标志或条件代码寄存器被合并在一起，使得当执行计算指令时，CISC指令和RISC指令将隐含地更新相同的合并的标志寄存器。 RISC和CISC寄存器被折叠在一起，使得CISC标志位于寄存器的一端，而频繁使用的RISC标志位于另一端，但RISC指令可以读或写合并寄存器中的任何位。 CISC代码段基地址存储在RISC分支计数寄存器中，而CISC浮点指令地址存储在RISC分支链路寄存器中。通用寄存器（GPR）也被合并在一起，允许CISC程序将数据传递到RISC程序，只需将其GPR，切换控制之一写入RISC程序，读取其中一个GPR的RISC程序即可与CISC程序写入的CISC GPR合并并对应。

9. 发明授权

US5685009A Shared floating-point registers and register port-pairing in a dual-architecture CPU 失效
标题翻译：共享浮点寄存器和注册端口配对在双架构CPU中
公开(公告)号：US5685009A
公开(公告)日：1997-11-04
申请号：US564719
申请日：1995-11-29
申请人： James S. Blomgren , David E. Richter , Cheryl Senter Brashears
发明人： James S. Blomgren , David E. Richter , Cheryl Senter Brashears
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/455
CPC分类号： G06F9/30101 , G06F9/30014 , G06F9/30094 , G06F9/30112 , G06F9/3013 , G06F9/30196 , G06F9/3861 , G06F9/45554
摘要： A dual-instruction-set central processing unit (CPU) is capable of executing floating point instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Floating point data is transferred from a CISC program to a RISC program running on the CPU by using shared floating point registers. The architecturally-defined floating point registers in the CISC instruction set are merged or folded into some of the architecturally-defined floating point registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the floating-point exception-mask and flags registers defined by each architecture are merged together so that CISC instructions and RISC instructions implicitly update the same merged flags register when executing floating point instructions. The RISC and CISC registers are folded together so that the CISC flags and RISC flags with the same function are merged to the same register bit. The floating-point data registers are also merged together, allowing a CISC program to pass floating-point data to a RISC program merely by writing one of its floating-point data registers, switching control to the RISC program, and the RISC program reading one of its floating-point data registers that is merged with and corresponds to the CISC floating-point data register that was written to by the CISC program. An extended-precision CISC data format is supported by pairing two of the RISC-size floating-point data registers.
摘要翻译：双指令集中央处理单元（CPU）能够执行来自精简指令集计算机（RISC）指令集和复指令集计算机（CISC）指令集的浮点指令。浮点数据通过使用共享浮点寄存器从CISC程序传送到运行在CPU上的RISC程序。 CISC指令集中的体系结构定义的浮点寄存器被合并或折叠成RISC体系结构中的一些体系结构定义的浮点寄存器，以便这两个指令集共享这些合并的寄存器。特别地，由每个架构定义的浮点异常掩码和标志寄存器被合并在一起，使得当执行浮点指令时，CISC指令和RISC指令隐含地更新相同的合并标志寄存器。将RISC和CISC寄存器折叠在一起，使具有相同功能的CISC标志和RISC标志被合并到相同的寄存器位。浮点数据寄存器也被合并在一起，允许CISC程序仅通过将其浮点数据寄存器之一写入RISC程序，将切换控制写入RISC程序，读取RISC程序其浮点数据寄存器与CISC程序写入的CISC浮点数据寄存器合并并对应。通过配置两个RISC大小的浮点数据寄存器来支持扩展精度的CISC数据格式。

10. 发明授权

US5781457A Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU 失效
标题翻译：在双ALU的矢量复用器中执行的两个指令集的合并/掩码，旋转/移位和布尔运算
公开(公告)号：US5781457A
公开(公告)日：1998-07-14
申请号：US649116
申请日：1996-05-14
申请人： Earl T. Cohen , James S. Blomgren , David E. Richter
发明人： Earl T. Cohen , James S. Blomgren , David E. Richter
IPC分类号： G06F7/575 , G06F7/76 , G06F7/38
CPC分类号： G06F7/764 , G06F7/575 , G06F7/762
摘要： A Boolean logic unit (BLU) features a vectored mux. Boolean instructions are executed by applying operands to the select inputs but truth-table signals to the data inputs. Merge and mask operations are performed by reversing the connection and inputting the operands to the data inputs but applying a merge mask to the select inputs. A byte-spreader copies byte or 16-bit operands to 32-bits before being rotated and merged by the vectored mux. A rotator is used to rotate an operand before being applied to the data input of the vectored mux so that compound rotate-merge operations can be executed in a single step through the vectored mux. A carry flag may also be merged in during a multi-step bit-test instruction. Complex CISC instructions such as rotate-through-carry and shift-double are executed in multiple steps on the vectored mux. Intermediate results are stored in the multiplier-quotient temporary registers which are normally used for multiply and divide instructions. A RISC ALU using the vectored mux BLU is modified only slightly to support execution of CISC instructions. Merge, mask, rotate, shift, and Boolean operations of both RISC and CISC instruction sets are executed in the same ALU because of the inherent flexibility of the vectored mux architecture.
摘要翻译：布尔逻辑单元（BLU）具有向量多路复用器。布尔指令通过将操作数应用于选择输入而实际表信号到数据输入来执行。通过反转连接并将操作数输入到数据输入，但将合并掩码应用于选择输入来执行合并和掩码操作。字节扩展器将字节或16位操作数复制到32位，然后由矢量复用器旋转并合并。旋转器用于在施加到向量多路复用器的数据输入之前旋转操作数，以便可以通过向量多路复用器在单个步骤中执行复合旋转合并操作。进位标志也可以在多步位测试指令期间被合并。复杂的CISC指令，例如旋转进位和移位双精度在多个步骤中被执行。中间结果存储在通常用于乘法和除法指令的乘法器商临时寄存器中。使用向量复用器BLU的RISC ALU仅稍微修改以支持执行CISC指令。 RISC和CISC指令集的合并，掩码，旋转，移位和布尔运算都由相同的ALU执行，因为矢量多路复用器架构具有固有的灵活性。

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