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1. 发明申请

US20070071155A1 Information handling system capable of detecting frequency lock of signals downstream from a signal synthesized by frequency synthesizer 失效
标题翻译：信号处理系统能够检测由频率合成器合成的信号下行信号的频率锁定
公开(公告)号：US20070071155A1
公开(公告)日：2007-03-29
申请号：US11236834
申请日：2005-09-27
申请人： David Boerstler , Matthew Fernsler , Eskinder Hailu , Jieming Qi , Mack Riley
发明人： David Boerstler , Matthew Fernsler , Eskinder Hailu , Jieming Qi , Mack Riley
IPC分类号： H04B17/00 , H03D3/24
CPC分类号： G06F1/10 , H03L7/095
摘要： An information handling system including a frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译：公开了一种包括频率合成器锁定检测系统的信息处理系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

2. 发明申请

US20070071154A1 Method and apparatus for detecting frequency lock in a system including a frequency synthesizer 失效
标题翻译：用于检测包括频率合成器的系统中的频率锁定的方法和装置
公开(公告)号：US20070071154A1
公开(公告)日：2007-03-29
申请号：US11236658
申请日：2005-09-27
申请人： David Boerstler , Matthew Fernsler , Eskinder Hailu , Jieming Qi , Mack Riley
发明人： David Boerstler , Matthew Fernsler , Eskinder Hailu , Jieming Qi , Mack Riley
IPC分类号： H03D3/24
CPC分类号： H03L7/093 , H03L7/095
摘要： A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
摘要翻译：公开了一种频率合成器锁定检测系统，其将分频网络上的频率合成器输出信号分配到一个或多个接收器电路。分配网络可能表现出延迟和其他失真，这些失真可能导致下游信号到达接收器电路，同时使用频率合成器输出信号和控制合成器输出信号频率的参考时钟信号来失去频率锁定。锁定检测系统测试下行信号以确定下游信号是否相对于确定频率合成器的工作频率的参考时钟呈现锁定。以这种方式，可以在一个实施例中精确地评估下行信号到参考时钟信号的锁定。

3. 发明申请

US20070236266A1 APPARATUS AND METHOD FOR EXTRACTING A MAXIMUM PULSE WIDTH OF A PULSE WIDTH LIMITER 失效
标题翻译：提取脉冲宽度极限的最大脉冲宽度的装置和方法
公开(公告)号：US20070236266A1
公开(公告)日：2007-10-11
申请号：US11278842
申请日：2006-04-06
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/1534 , H03K5/156 , H03K2005/00293
摘要： An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells utilized in the circuit arrangement described in commonly assigned and co-pending U.S. patent application Ser. No. 11/109,090 (hereafter referred to as the '090 application). The elimination of these delay cells is made possible in one illustrative embodiment by replacing an OR gate in the circuit configuration of the '090 application with an edge triggered re-settable latch. The replacement of the OR gate with the edge triggered re-settable latch reduces the amount of chip area used in addition to the power consumption of the circuit.
摘要翻译：提供了一种用于提取脉冲宽度限制器的最大脉冲宽度的装置和方法。说明性实施例的装置和方法使用被配置为消除在共同转让和共同未决的美国专利申请Ser中描述的电路装置中使用的大多数延迟单元的电路来执行这种提取。第11 / 109,090号（以下简称“090”）。在一个说明性实施例中，通过用'边缘触发的可重新设定的锁存器'替换'090应用的电路配置中的或门，可以消除这些延迟单元。利用边沿触发的可重新设置的锁存器替换或门可以减少除了电路功耗之外使用的芯片面积。

4. 发明申请

US20070126475A1 Method and Apparatus for Semi-Automatic Extraction and Monitoring of Diode Ideality in a Manufacturing Environment 审中-公开
标题翻译：在制造环境中半自动提取和监控二极管理想的方法和装置
公开(公告)号：US20070126475A1
公开(公告)日：2007-06-07
申请号：US11466542
申请日：2006-08-23
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K19/173
CPC分类号： G01R31/2632
摘要： A method, an apparatus, and a computer program are provided for the semi-automatic extraction of an ideality factor of a diode. Traditionally, current/voltage curves for diodes, which provided a basis for extrapolating the ideality factors, had to be determined by hand. By employing a thermal voltage proportional to absolute temperature (PTAT) generator in conjunction with an extraction mechanism, the ideality factor can be extracted in an semi-automatic manner. Therefore, a reliable, quick, and less expensive device can be employed to improve measurements of ideality factors.
摘要翻译：提供了一种半自动提取二极管理想因子的方法，装置和计算机程序。传统上，二极管的电流/电压曲线为理想因素外推提供了基础，必须用手来确定。通过采用与绝对温度（PTAT）发生器成比例的热电压与提取机制，理想因子可以半自动提取。因此，可以采用可靠，快速和便宜的装置来改善理想因素的测量。

5. 发明申请

US20070079197A1 Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance 有权
标题翻译：用于自动自校准占空比电路以实现最大芯片性能的装置和方法
公开(公告)号：US20070079197A1
公开(公告)日：2007-04-05
申请号：US11242677
申请日：2005-10-04
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G01R31/28
CPC分类号： H03K5/1565 , G01R31/31727 , G01R31/3187
摘要： An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance are provided. A chip level built-in circuit that automatically calibrates the duty cycle correction (DCC) circuit setting for each chip is provided. This chip level built-in circuit includes a clock generation macro unit, a simple duty cycle correction (DCC) circuit, an array slice and built-in self test unit, and a DCC circuit controller. Results of a built-in self test, i.e. pass or fail, of an array are provided to the DCC circuit controller. If the result of the built-in self test is a pass, then the current DCC circuit controller's DCC control bit setting is set as the setting for the chip. If the result from the built-in self test is a fail, the DCC circuit controller's DCC control bits setting is incremented to a next setting and the self-test is performed again.
摘要翻译：提供一种用于自动校准占空比电路以实现最大性能的装置和方法。提供了自动校准每个芯片的占空比校正（DCC）电路设置的芯片级内置电路。该芯片级内置电路包括时钟生成宏单元，简单占空比校正（DCC）电路，阵列片和内置自检单元以及DCC电路控制器。向DCC电路控制器提供阵列的内置自检，即通过或失败的结果。如果内置自检的结果是通过，则将当前DCC电路控制器的DCC控制位设置设置为芯片的设置。如果内置自检的结果为失败，DCC电路控制器的DCC控制位设置将增加到下一个设置，并再次执行自检。

6. 发明申请

US20060232310A1 System and method for on/off-chip characterization of pulse-width limiter outputs 失效
标题翻译：用于脉宽限幅器输出的片外特性的系统和方法
公开(公告)号：US20060232310A1
公开(公告)日：2006-10-19
申请号：US11109090
申请日：2005-04-19
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： H03K5/156 , G01R31/31708 , G01R31/31725 , H03K5/05 , H03K5/26
摘要： The present invention provides for a method for characterization of pulse-width limiter outputs. A known clock signal is received. A pulse width of the received known clock signal is limited through a first pulse-width limiter to generate a first intermediate signal. The first intermediate signal is delayed by a known amount to generate a first delayed signal. The first intermediate signal is inverted to generate a first inverted signal. A pulse width of the first inverted signal is limited through a second pulse-width limiter to generate a second intermediate signal. The second intermediate signal is delayed by a known amount to generate a second delayed signal. A logic OR operation is performed on the first delayed signal and the second delayed signal to generate a clock out signal.
摘要翻译：本发明提供了用于表征脉冲宽度限制器输出的方法。接收已知的时钟信号。所接收的已知时钟信号的脉冲宽度通过第一脉冲宽度限制器来限制，以产生第一中间信号。第一中间信号被延迟已知的量以产生第一延迟信号。第一中间信号被反相以产生第一反相信号。通过第二脉冲宽度限幅器限制第一反相信号的脉冲宽度以产生第二中间信号。第二中间信号被延迟已知的量以产生第二延迟信号。对第一延迟信号和第二延迟信号执行逻辑或运算以产生时钟输出信号。

7. 发明申请

US20080111604A1 DIGITAL CIRCUIT TO MEASURE AND/OR CORRECT DUTY CYCLES 有权
标题翻译：数字电路测量和/或校正责任周期
公开(公告)号：US20080111604A1
公开(公告)日：2008-05-15
申请号：US12014501
申请日：2008-01-15
申请人： David Boerstler , Eskinder Hailu , Byron Krauter , Kazuhiko Miki , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Byron Krauter , Kazuhiko Miki , Jieming Qi
IPC分类号： H03K3/017
CPC分类号： G06F1/10 , H03K5/1565
摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.
摘要翻译：提供了一种方法，装置和计算机程序来测量和/或校正占空比。各种信号的占空比，特别是时钟信号是很重要的。然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

8. 发明申请

US20070075370A1 Thermal sensing method and apparatus using existing ESD devices 有权
标题翻译：使用现有ESD器件的热感测方法和设备
公开(公告)号：US20070075370A1
公开(公告)日：2007-04-05
申请号：US11242675
申请日：2005-10-04
申请人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H01L23/62
CPC分类号： G01K7/01 , G01K2217/00
摘要： The present invention provides a method, an apparatus, and a computer program product for measuring the temperature of a microprocessor through the use of ESD circuitry. The present invention uses diodes and an I/O pad within ESD circuits to determine the temperature at the location of the ESD circuitry. First, a current measuring device connects to a diode. A user or a computer program disables the protected component or circuitry, and subsequently applies a predetermined voltage to the I/O pad. This creates a reverse saturation current through the diode, which is measured by the current measuring device. From this current the user or a computer program determines the temperature of the microprocessor at the diode through the use of a graphical representation of diode reverse saturation current and corresponding temperature.
摘要翻译：本发明提供了一种通过使用ESD电路来测量微处理器的温度的方法，装置和计算机程序产品。本发明在ESD电路中使用二极管和I / O焊盘来确定ESD电路位置处的温度。首先，电流测量装置连接到二极管。用户或计算机程序禁用受保护的组件或电路，然后将预定电压施加到I / O焊盘。这通过二极管产生反向饱和电流，由电流测量装置测量。从该电流，用户或计算机程序通过使用二极管反向饱和电流和相应温度的图形表示来确定微处理器在二极管处的温度。

9. 发明申请

US20060212739A1 Digital circuit to measure and/or correct duty cycles 有权
标题翻译：用于测量和/或校正占空比的数字电路
公开(公告)号：US20060212739A1
公开(公告)日：2006-09-21
申请号：US11082973
申请日：2005-03-17
申请人： David Boerstler , Eskinder Hailu , Byron Krauter , Kazuhiko Miki , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Byron Krauter , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , H03K5/1565
摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.
摘要翻译：提供了一种方法，装置和计算机程序来测量和/或校正占空比。各种信号的占空比，特别是时钟信号是很重要的。然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

10. 发明申请

US20060190746A1 System and method for automatic calibration of a reference voltage 失效
标题翻译：用于自动校准参考电压的系统和方法
公开(公告)号：US20060190746A1
公开(公告)日：2006-08-24
申请号：US11065549
申请日：2005-02-24
申请人： David Boerstler , Eskinder Hailu , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： A system and system for automatic voltage calibration is presented. A voltage calibration system includes three main units, which are a voltage level trimming unit, a trim detection unit, and a trim control unit. The three units work in conjunction with each other during a trimming operation in order to identify a tap voltage that is closest to a target voltage. In one embodiment, the voltage calibration system may be used to calibrate a voltage regulator. Upon commencement of calibration, the voltage regulator's feedback loop is open, and the target voltage is selected as the input for the feedback port of the amplifier. The voltage regulator serves as a voltage comparator that compares each tap voltage to the target voltage. When the calibration is complete, regulator's feedback loop is closed and the closest tap voltage to the target voltage is used as the regulator's input.
摘要翻译：提出了一种用于自动电压校准的系统和系统。电压校准系统包括三个主要单元，它们是电压调整单元，微调检测单元和微调控制单元。三个单元在微调操作期间相互协调工作，以便识别最接近目标电压的抽头电压。在一个实施例中，电压校准系统可用于校准电压调节器。校准开始后，电压调节器的反馈回路打开，目标电压被选为放大器反馈端口的输入。电压调节器用作将每个抽头电压与目标电压进行比较的电压比较器。当校准完成时，调节器的反馈回路闭合，并将最接近目标电压的分接电压用作调节器的输入。

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