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1. 发明申请

US20080068238A1 Entry/Exit Control To/From a Low Power State in a CPU with an Unprotected Pipeline 审中-公开
标题翻译：在具有无保护管道的CPU中进入/退出控制到低功耗状态
公开(公告)号：US20080068238A1
公开(公告)日：2008-03-20
申请号：US11855585
申请日：2007-09-14
申请人： David Bell , Timothy Anderson , Lewis Nardini , Jose Flores , Anthony Lell
发明人： David Bell , Timothy Anderson , Lewis Nardini , Jose Flores , Anthony Lell
IPC分类号： H03M1/00
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic blocks and memory during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.
摘要翻译：嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑块和存储器的低功耗状态。要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。

2. 发明申请

US20070094537A1 Address Range Comparator for Detection of Multi-Size Memory Accesses With Data Matching Qualification and Full or Partial Overlap 有权
标题翻译：用于通过数据匹配鉴定和全部或部分重叠检测多尺寸存储器访问的地址范围比较器
公开(公告)号：US20070094537A1
公开(公告)日：2007-04-26
申请号：US11566772
申请日：2006-12-05
申请人： Jose Flores , Lewis Nardini , Maria Gill
发明人： Jose Flores , Lewis Nardini , Maria Gill
IPC分类号： G06F11/00
CPC分类号： G06F11/3648 , G01R31/31703 , G01R31/31705 , G06F11/3656
摘要： An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.
摘要翻译：存储器访问地址比较器包括将输入存储器访问地址与相应的参考地址进行比较的两个比较器。比较器根据可选择的标准产生匹配指示，例如地址大小，全部或部分重叠，大于，小于，等于，不等于，小于等于并且大于或等于，并且可以是选择性地链接。输入多路复用器允许存储器访问地址总线选择。比较器输出可以选择性地依赖于相应的数据匹配。参考地址，比较数据和控制功能通过中央处理单元可访问存储器映射寄存器使能。

3. 发明申请

US20060282706A1 Program Counter Range Comparator With Equality, Greater Than, Less Than and Non-Equal Detection Modes 有权
标题翻译：程序计数器范围比较器具有平等，大于，小于和等于不等的检测模式
公开(公告)号：US20060282706A1
公开(公告)日：2006-12-14
申请号：US11467727
申请日：2006-08-28
申请人： Jose Flores , Lewis Nardini , Maria Gill
发明人： Jose Flores , Lewis Nardini , Maria Gill
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.
摘要翻译：程序计数器地址比较器包括将输入程序计数器地址与各个参考地址进行比较的两个比较器。比较器产生可选标准的匹配指示，例如大于，小于，等于，不等于，小于或等于，且大于或等于，并且可以选择性地链接。输入多路复用器允许选择程序计数器地址总线或辅助地址总线。参考地址和控制功能通过中央处理单元可访问存储器映射寄存器使能。

4. 发明申请

US20060288254A1 Multi-Port Trace Data Handling 有权
标题翻译：多端口跟踪数据处理
公开(公告)号：US20060288254A1
公开(公告)日：2006-12-21
申请号：US11467735
申请日：2006-08-28
申请人： Manisha Agarwala , Lewis Nardini , John Johnsen , Maria Gill , Jose Flores
发明人： Manisha Agarwala , Lewis Nardini , John Johnsen , Maria Gill , Jose Flores
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.
摘要翻译：跟踪数据压缩的方法在第一端口上接收跟踪数据，而第二端口存储先前的数据值。如果仅在一个端口上接收到跟踪数据，则该跟踪数据作为当前跟踪数据与存储的数据值之间的匹配和非匹配部分的指示以及当前跟踪数据的不匹配部分在一个端口上发送港口。如果在两个端口上都接收到跟踪数据，则相对于先前存储的值传输第一个端口跟踪数据，并且相对于第一个端口跟踪数据传输第二个端口跟踪数据。在任一端口上的跟踪数据的每次启动或终止时，存储的先前数据被重置为零。如果没有接收到第二个端口值，则将存储的先前值设置为第二个端口值或第一个端口值。

5. 发明授权

US08655637B2 Address range comparator for detection of multi-size memory accesses with data matching qualification and full or partial overlap 有权
标题翻译：地址范围比较器，用于检测具有数据匹配限定和全部或部分重叠的多尺寸存储器访问
公开(公告)号：US08655637B2
公开(公告)日：2014-02-18
申请号：US11566772
申请日：2006-12-05
申请人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
发明人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
IPC分类号： G06F9/455
CPC分类号： G06F11/3648 , G01R31/31703 , G01R31/31705 , G06F11/3656
摘要： An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.
摘要翻译：存储器访问地址比较器包括将输入存储器访问地址与相应的参考地址进行比较的两个比较器。比较器根据可选择的标准产生匹配指示，例如地址大小，全部或部分重叠，大于，小于，等于，不等于，小于等于并且大于或等于，并且可以是选择性地链接。输入多路复用器允许存储器访问地址总线选择。比较器输出可以选择性地依赖于相应的数据匹配。参考地址，比较数据和控制功能通过中央处理单元可访问存储器映射寄存器使能。

6. 发明授权

US07925687B2 Reporting a saturated counter value 有权
标题翻译：报告饱和计数器值
公开(公告)号：US07925687B2
公开(公告)日：2011-04-12
申请号：US11383335
申请日：2006-05-15
申请人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
发明人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
IPC分类号： G06F7/38
CPC分类号： G06F11/261
摘要： A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.
摘要翻译：饱和计数将接收的事件信号计数到第一预定数量。溢出计数器计数溢出到第二预定数量。当溢出计数达到第二个预定数量时，计数器指示溢出计数不为零并饱和，并以最大计数停止计数。可以通过寄存器读取操作读取计数器。第一预定位数和第二预定位数之和为8位的整数倍的总和。

7. 发明授权

US07475172B2 Progressive extended compression mask for dynamic trace 有权
标题翻译：逐行扩展压缩掩码，用于动态跟踪
公开(公告)号：US07475172B2
公开(公告)日：2009-01-06
申请号：US11566751
申请日：2006-12-05
申请人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
发明人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
IPC分类号： G06F3/00 , G06F13/12 , G06F9/455 , G01R31/28
CPC分类号： G06F11/3636 , G06F11/3476
摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.
摘要翻译：本发明通过将当前跟踪地址的各个字节与存储的先前跟踪地址进行比较来提供跟踪地址压缩。只有当前跟踪地址中与存储的先前跟踪地址不匹配或者比当前跟踪地址中与存储的先前跟踪地址不匹配的任何部分不太重要的最低有效字节被传送。这有时会减少需要传输的数据量。如果存在完全不匹配，则可以使用当前跟踪地址更新先前的跟踪地址。

8. 发明申请

US20070055855A1 Tracing through reset 有权
公开(公告)号：US20070055855A1
公开(公告)日：2007-03-08
申请号：US11359158
申请日：2006-02-21
申请人： Manisha Agarwala , Lewis Nardini
发明人： Manisha Agarwala , Lewis Nardini
IPC分类号： G06F15/177
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.

9. 发明授权

US07165018B2 Address range comparator for detection of multi size memory accesses with data matching qualification and full or partial overlap 有权
标题翻译：地址范围比较器，用于检测具有数据匹配限定和全部或部分重叠的多尺寸存储器访问
公开(公告)号：US07165018B2
公开(公告)日：2007-01-16
申请号：US10301887
申请日：2002-11-22
申请人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
发明人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
IPC分类号： G06F9/455
CPC分类号： G06F11/3648 , G01R31/31703 , G01R31/31705 , G06F11/3656
摘要： An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.
摘要翻译：存储器访问地址比较器包括将输入存储器访问地址与相应的参考地址进行比较的两个比较器。比较器根据可选择的标准产生匹配指示，例如地址大小，全部或部分重叠，大于，小于，等于，不等于，小于等于并且大于或等于，并且可以是选择性地链接。输入多路复用器允许存储器访问地址总线选择。比较器输出可以选择性地依赖于相应的数据匹配。参考地址，比较数据和控制功能通过中央处理单元可访问存储器映射寄存器使能。

10. 发明申请

US20070011662A1 Tracing Program Counter Addresses Using Native Program Counter Format and Instruction Count Format 有权
标题翻译：跟踪程序计数器地址使用本机程序计数器格式和指令计数格式
公开(公告)号：US20070011662A1
公开(公告)日：2007-01-11
申请号：US11383337
申请日：2006-05-15
申请人： Manisha Agarwala , Bryan Thome , John Johnsen , Gary Swoboda , Lewis Nardini , Maria Gill
发明人： Manisha Agarwala , Bryan Thome , John Johnsen , Gary Swoboda , Lewis Nardini , Maria Gill
IPC分类号： G06F9/44
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.
摘要翻译：在数据处理器中跟踪程序计数器活动的方法周期性地发送包括当前程序计数器地址的程序计数器同步点。在同步点之间，程序计数器地址由相对于最后一个程序计数器同步点的程序计数器偏移指示。程序计数器偏移作为整数个预定位数的部分发送。程序计数器的同步点经常被传送到足够多的程序计数器偏移量至少比程序计数器地址少一个部分。

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